Difference between revisions of "CoE 197U S2 AY 2023-2024"

From Microlab Classes
Jump to navigation Jump to search
 
(29 intermediate revisions by 5 users not shown)
Line 36: Line 36:
 
* CoE 197U Orientation
 
* CoE 197U Orientation
 
* [[CoE197U_2s2324 Introduction | Introduction]]
 
* [[CoE197U_2s2324 Introduction | Introduction]]
 +
* [[CoE 197U IC Fabrication | IC Fabrication]]
 
|  
 
|  
 
* Set class expectations, discuss grading system
 
* Set class expectations, discuss grading system
 
* Introduction to CoE 197U
 
* Introduction to CoE 197U
 +
* Identify the key characteristics and non-idealities of a CMOS fabrication process.
 
|  
 
|  
 +
* Video: Silicon Run I (1996) [https://www.youtube.com/watch?v=3XTWXRj24GM Youtube link]
 
|
 
|
 
* Lab orientation
 
* Lab orientation
Line 46: Line 49:
 
|  
 
|  
 
''Feb 19-23''
 
''Feb 19-23''
−
* [[CoE 197U IC Fabrication | IC Fabrication]]
+
* [[CoE197U_2s2324 Scaling | Scaling]]
−
* [[CoE 197U Scaling | Scaling]]
+
* [[CoE 197U The MOS Switch | The MOS Switch]]
 +
* The MOS Transistor
 
|  
 
|  
−
* Identify the key characteristics and non-idealities of a CMOS fabrication process.
+
* Analyze how key characteristics and non-idealities change the characteristics of the devices that will be built on it.
−
* Analyze how these key characteristics and non-idealities change the characteristics of the devices that will be built on it.
 
 
|  
 
|  
−
* Video: Silicon Run I (1996) [https://www.youtube.com/watch?v=3XTWXRj24GM Youtube link]
+
* Slides: [[https://drive.google.com/file/d/1oaz6MnWQzn23AMP540hw3NY0A0iIl6BS/view?usp=sharing Scaling]]
−
* Paolo Gargini's [https://www.dropbox.com/s/6eskh6bwdcuzpsa/1507_11_Paolo%20Overview_Out.pdf presentation] from the 2015 [http://www.itrs2.net/ International Technology Roadmap for Semiconductors] (ITRS) Summer Meeting.
+
* Video: [[https://drive.google.com/file/d/1MFGDiu4yEPq_JPuy4yPHi_vgSa-B57g-/view?usp=sharing Scaling recoding]]
 +
* Slides: [[https://drive.google.com/file/d/1NBkPPA3f4Lswaz9cEI2dqESwNz7jRwmi/view?usp=sharing MOS]]  
 
|
 
|
−
* [[CoE197U-A1.1]]: IC Fabrication and Scaling
 
 
* [https://drive.google.com/file/d/18IK7RB_BFwWqOnByLnNsgbLaTz4AtvAE/view?usp=sharing Lab 01]: Introduction to Digital IC Design (MOS Characterization)
 
* [https://drive.google.com/file/d/18IK7RB_BFwWqOnByLnNsgbLaTz4AtvAE/view?usp=sharing Lab 01]: Introduction to Digital IC Design (MOS Characterization)
 
|-
 
|-
Line 61: Line 64:
 
|  
 
|  
 
''Feb 26-Mar 1''
 
''Feb 26-Mar 1''
−
* [[CoE 197U The MOS Transistor | The MOS Transistor]]
 
−
* [[CoE 197U The MOS Switch | The MOS Switch]]
 
 
* [[CoE 197U CMOS Inverter | The CMOS Inverter]]
 
* [[CoE 197U CMOS Inverter | The CMOS Inverter]]
 +
* [[ CoE 197U CMOS Gates | Static CMOS Gates ]]
 
|  
 
|  
 
* Simplify the analysis of a CMOS inverter using switch-level transistor models.
 
* Simplify the analysis of a CMOS inverter using switch-level transistor models.
 
* Determine key CMOS inverter metrics and understand their significance in the analysis and design process.
 
* Determine key CMOS inverter metrics and understand their significance in the analysis and design process.
 +
* Design CMOS static gates
 
|  
 
|  
−
* Slides: MOS [[https://drive.google.com/file/d/1H-aBeApfPlgFNqAMoMqIDZSbyDmwHFPf/view?usp=sharing PDF]]
+
* Slides: [[https://drive.google.com/file/d/1NEDBYESf-WXmC5CCIUn5uCODawGLqER6/view?usp=sharing CMOS Inverter]]  
−
* Slides: CMOS Inverter [[https://drive.google.com/file/d/1H4Dt_YkLFLWvAVurp7ZxcXbJAPw6frR5/view?usp=sharing PDF]]
+
* Slides: [[https://drive.google.com/file/d/1NPGJfJ8c9D16ld7i_1xBafYmA1cOLV3K/view?usp=sharing CMOS Gates]]  
−
* Recording: Module Discussion [[https://drive.google.com/file/d/1H5yoNWBSQfp_TSfS6voFygigZTX6G97F/view?usp=sharing Video]]
+
* Video: [[https://drive.google.com/file/d/1q-pEBVprOHOdY9bikkkCgZUCTpUvWM3s/view?usp=sharing CMOS Gates Lecture]]
 
|
 
|
 
* [https://drive.google.com/file/d/18UYFxIaRGhsmvG85DYrZjySjsFcbuUlm/view?usp=sharing Lab 02]: CMOS Inverter
 
* [https://drive.google.com/file/d/18UYFxIaRGhsmvG85DYrZjySjsFcbuUlm/view?usp=sharing Lab 02]: CMOS Inverter
Line 77: Line 80:
 
|  
 
|  
 
''Mar 4-8''
 
''Mar 4-8''
−
* [[ CoE 197U CMOS Gates | Static CMOS Gates ]]
 
 
* [[ CoE 197U Logical Effort | Logical Effort and Delay ]]
 
* [[ CoE 197U Logical Effort | Logical Effort and Delay ]]
 
|  
 
|  
−
* Design CMOS static gates
 
 
* Estimate delays of cascaded logic gates
 
* Estimate delays of cascaded logic gates
 
* Design multistage networks for optimal speed
 
* Design multistage networks for optimal speed
 
|  
 
|  
−
* Slides: CMOS Gates [[https://drive.google.com/file/d/10McCC1megDnllbIMj7rdtBlyZB84QVBh/view?usp=sharing PDF]]
+
* Slides: Logical Effort [[https://drive.google.com/file/d/1cyHP4BSd4aknLecuQGql_jLGo-GFqDsq/view?usp=sharing PDF]]
−
* Slides: Logical Effort [[https://drive.google.com/file/d/10dGqE_NolixkYaL7aUWMlwPaIILprEFg/view?usp=sharing PDF]]
 
−
* Additional Slides: LE Example [[https://drive.google.com/file/d/1IvgU-3yIFlPBbj0PAdfdnyrPYkas3qnf/view?usp=sharing PDF]]
 
 
|
 
|
 
<!-- * [[CoE197U-A3.1]]: Logical Effort -->
 
<!-- * [[CoE197U-A3.1]]: Logical Effort -->
−
* [https://drive.google.com/file/d/1IgdNWWsXWqQegJP914KjZ7m4zVZ5LEQo/view?usp=sharing HW] Module 3 HW (final extension May 5)
+
* [https://drive.google.com/file/d/18_k97CdiAwOJ8LjWhrWcoZDJZjG6fyq7/view?usp=sharing Lab 03]: Static CMOS Gates and Delay Optimization
−
* [https://drive.google.com/file/d/18_k97CdiAwOJ8LjWhrWcoZDJZjG6fyq7/view?usp=sharing Lab 03]: Static CMOS Gates
 
 
|-
 
|-
 
| style="text-align:center;" | 4
 
| style="text-align:center;" | 4
Line 96: Line 94:
 
''Mar 11-15''
 
''Mar 11-15''
 
* [[ CoE 197U Power and Energy | Power and Energy ]]
 
* [[ CoE 197U Power and Energy | Power and Energy ]]
−
* Optional: [[ CoE 197U Interconnects | Interconnects ]]
+
* [[ CoE 197U Interconnects | Interconnects ]]
 
|  
 
|  
 
* Identify sources of power and energy consumption in digital circuits
 
* Identify sources of power and energy consumption in digital circuits
Line 105: Line 103:
 
* Slides: Interconnects [PDF]
 
* Slides: Interconnects [PDF]
 
|
 
|
−
* [https://drive.google.com/file/d/18gbBWwj7zG1ZT50RKUn0-Tzt9UlY54cI/view?usp=sharing Lab 04]: Delay Optimization and Considerations in Digital Design
+
* [https://drive.google.com/file/d/18gbBWwj7zG1ZT50RKUn0-Tzt9UlY54cI/view?usp=sharing Lab 04]: Considerations in Digital Design
 
|-
 
|-
 
| style="text-align:center;" | 5
 
| style="text-align:center;" | 5
Line 124: Line 122:
 
|
 
|
 
<!-- * [[CoE197U-A5.1]]: Timing -->
 
<!-- * [[CoE197U-A5.1]]: Timing -->
−
* [https://drive.google.com/file/d/18xW5VQe0fCq5LPwyIVDOGgq52GE9xU0-/view?usp=sharing Lab 05]: Memory and Timing
+
* [https://drive.google.com/file/d/18xW5VQe0fCq5LPwyIVDOGgq52GE9xU0-/view?usp=sharing Lab (Optional)]: Memory and Timing
 
|-
 
|-
 
| style="text-align:center;" colspan="5" | ''March 23: Long Exam 1''
 
| style="text-align:center;" colspan="5" | ''March 23: Long Exam 1''
Line 132: Line 130:
 
| style="text-align:center;" | 6
 
| style="text-align:center;" | 6
 
|
 
|
−
''Apr 8-12''
+
''Apr 12-19''
 
* MOS Amplifiers: DC and AC Analysis
 
* MOS Amplifiers: DC and AC Analysis
 
|
 
|
 +
* Revisit transistor models used for analog circuit design.
 +
* Identify the limitations of the square-law model.
 +
* Learn the model-based design methodology.
 
* Determine the DC operating point of MOS amplifiers.
 
* Determine the DC operating point of MOS amplifiers.
 
* Extract the MOS small-signal parameters depending on the DC operating point.
 
* Extract the MOS small-signal parameters depending on the DC operating point.
Line 141: Line 142:
 
* Identify the appropriate application of a MOS amplifier topology based on its two-port parameters.
 
* Identify the appropriate application of a MOS amplifier topology based on its two-port parameters.
 
|
 
|
−
* Slides: DC and AC Analysis [[https://drive.google.com/file/d/1J5bNkvjyJ5dF0HWpcLABiQq9WOlnyqje/view?usp=sharing PDF]]
+
* Slides: Transistor Models [[https://drive.google.com/file/d/1bOu5lnZ_rLJ4OZhgYP5YuY4pjisF-DD9/view?usp=share_link PDF]]
−
* Videos: [https://www.youtube.com/watch?v=4tEYeFiYwWI&list=PL4if6jkKNTz9RgsB4Gq_g374b4oLYOAeH&index=1 Part 1] [https://www.youtube.com/watch?v=lD7ejAl4Ue4&list=PL4if6jkKNTz9RgsB4Gq_g374b4oLYOAeH&index=2 Part 2]
+
* Slides: Model-Based Design [[https://drive.google.com/file/d/10nPUor4fyzNAErXF0x6qPRcN0WQwx8ye/view?usp=share_link PDF]]
 +
* Slides: DC and AC Analysis of Single-Stage Amplifiers [[https://drive.google.com/file/d/1C_elBzuFBmMjaKRy3qqNFBTMVMrI4SR-/view?usp=share_link PDF]]
 +
* Old Slides: DC and AC Analysis [[https://drive.google.com/file/d/1J5bNkvjyJ5dF0HWpcLABiQq9WOlnyqje/view?usp=sharing PDF]]
 +
* Old Videos: [https://www.youtube.com/watch?v=4tEYeFiYwWI&list=PL4if6jkKNTz9RgsB4Gq_g374b4oLYOAeH&index=1 Part 1] [https://www.youtube.com/watch?v=lD7ejAl4Ue4&list=PL4if6jkKNTz9RgsB4Gq_g374b4oLYOAeH&index=2 Part 2]
 
|
 
|
−
* Lab 06: Introduction to Analog IC Design (MOS Characterization)  
+
* [https://drive.google.com/file/d/1bqUhc70NctPCtQSPmXyXw464hWxGXovM/view?usp=sharing Lab 05]: Introduction to Analog IC Design (MOS Transistor Characterization)
 
|-
 
|-
 
| style="text-align:center;" | 7
 
| style="text-align:center;" | 7
 
|
 
|
−
''Apr 15-19''
+
''Apr 22-26''
 
* MOS Amplifiers: Frequency Response
 
* MOS Amplifiers: Frequency Response
 
|
 
|
Line 155: Line 159:
 
* Estimate the dominant pole using ZVTCA.
 
* Estimate the dominant pole using ZVTCA.
 
|
 
|
−
* Slides: Frequency Response [[https://drive.google.com/file/d/1IA9OF95XS4FV852IuIpbY5iy1KquA4VI/view?usp=sharing PDF]]
+
* Slides: Frequency Response Part 1 [[https://drive.google.com/file/d/1LFjcJiXO_HwPl9Kf0rmpb5aiDiC3Tqdy/view?usp=share_link PDF]]
−
* Videos: [https://www.youtube.com/watch?v=1AzlCV_AXgg&list=PL4if6jkKNTz9RgsB4Gq_g374b4oLYOAeH&index=3 Part 1] [https://www.youtube.com/watch?v=I3I6CBye0rU&list=PL4if6jkKNTz9RgsB4Gq_g374b4oLYOAeH&index=4 Part 2] [https://www.youtube.com/watch?v=55w6EXRSR1M&list=PL4if6jkKNTz9RgsB4Gq_g374b4oLYOAeH&index=5 Part 3]
+
* Zoom recording: [[https://drive.google.com/file/d/1aKT6ynwsQkHdo019_4q7KvYskqTSui-b/view?usp=share_link LINK]]
 +
* Slides: Frequency Response Part 2 [[https://drive.google.com/file/d/18gUtmM2ptKRIFcCTBp4ICG9bX0IExMCq/view?usp=share_link PDF]]
 +
* Old Slides: Frequency Response [[https://drive.google.com/file/d/1IA9OF95XS4FV852IuIpbY5iy1KquA4VI/view?usp=sharing PDF]]
 +
* Old Videos: [https://www.youtube.com/watch?v=1AzlCV_AXgg&list=PL4if6jkKNTz9RgsB4Gq_g374b4oLYOAeH&index=3 Part 1] [https://www.youtube.com/watch?v=I3I6CBye0rU&list=PL4if6jkKNTz9RgsB4Gq_g374b4oLYOAeH&index=4 Part 2] [https://www.youtube.com/watch?v=55w6EXRSR1M&list=PL4if6jkKNTz9RgsB4Gq_g374b4oLYOAeH&index=5 Part 3]
 
|
 
|
−
* Lab 07: Common-Source Amplifier with Resistive Load
+
* [https://drive.google.com/file/d/1AAE2Sx7H9lD1hm93yGOU_3hv4TB5Px7m/view?usp=sharing Lab 06]: Common-Source Amplifier with Resistive Load
 
|-
 
|-
 
| style="text-align:center;" | 8
 
| style="text-align:center;" | 8
 
|
 
|
−
''Apr 22-26''
+
''May 3-8''
 
* Current Sources
 
* Current Sources
 
* High-Swing Current Sources
 
* High-Swing Current Sources
Line 170: Line 177:
 
* Analyze High-swing current sources
 
* Analyze High-swing current sources
 
|  
 
|  
−
* Slides: Current Sources [[https://drive.google.com/file/d/19jU1NupCk66ta6Q3tJyWFYDUagqaZCQs/view?usp=sharing PDF]] [[https://drive.google.com/file/d/1LQBAYGi4V2OVDtcDEwU78ianL_LD4PTk/view?usp=sharing Annotated PDF]]
+
* Old Slides: Current Sources [[https://drive.google.com/file/d/19jU1NupCk66ta6Q3tJyWFYDUagqaZCQs/view?usp=sharing PDF]] [[https://drive.google.com/file/d/1LQBAYGi4V2OVDtcDEwU78ianL_LD4PTk/view?usp=sharing Annotated PDF]]
−
* Slides: High-Swing Current Sources [[https://drive.google.com/file/d/15dsEE2jcVoUNasZmvCOlewN77UxfOieB/view?usp=sharing PDF]] [[https://drive.google.com/file/d/1jtwEvsdZ9uWTYQ969RcQXfwyGtOSCOSL/view?usp=sharing Annotated PDF]]
+
* Old Slides: High-Swing Current Sources [[https://drive.google.com/file/d/15dsEE2jcVoUNasZmvCOlewN77UxfOieB/view?usp=sharing PDF]] [[https://drive.google.com/file/d/1jtwEvsdZ9uWTYQ969RcQXfwyGtOSCOSL/view?usp=sharing Annotated PDF]]
−
* Videos: [https://drive.google.com/file/d/1vxGdeB_VRUoyA5G4XotYUWxmBPFhXjyN/view?usp=sharing Part 1] [https://drive.google.com/file/d/11cjEGTWBCXKZ92Op4luxM3MMGThBXPbH/view?usp=sharing Part 2]
+
* Old Videos: [https://drive.google.com/file/d/1vxGdeB_VRUoyA5G4XotYUWxmBPFhXjyN/view?usp=sharing Part 1] [https://drive.google.com/file/d/11cjEGTWBCXKZ92Op4luxM3MMGThBXPbH/view?usp=sharing Part 2]
 
|
 
|
−
* Lab 08: Current Sources
+
* [https://drive.google.com/file/d/17UnGEpTyjZ3IEvRpbRtyyBY0x-2QbV5x/view?usp=sharing Lab 07]: Current Sources
 
|-
 
|-
 
| style="text-align:center;" | 9
 
| style="text-align:center;" | 9
 
|  
 
|  
−
''Apr 29-May 3''
+
''May 10-15''
 
* [[ CoE 197U MOS Differential Pairs | MOS Differential Pairs ]]
 
* [[ CoE 197U MOS Differential Pairs | MOS Differential Pairs ]]
 
* [[ CoE 197U Two-Stage MOS Operational Transconductance Amplifiers | Two-Stage MOS OTA ]]
 
* [[ CoE 197U Two-Stage MOS Operational Transconductance Amplifiers | Two-Stage MOS OTA ]]
Line 187: Line 194:
 
* Analyze Miller Operational Amplifiers
 
* Analyze Miller Operational Amplifiers
 
|  
 
|  
−
* Slides: MOS Differential Pairs [[https://drive.google.com/file/d/10p4T9_5qMXiXPeVU0B0yHmzmtTabiQ43/view?usp=sharing PDF]]
+
* Old Slides: MOS Differential Pairs [[https://drive.google.com/file/d/10p4T9_5qMXiXPeVU0B0yHmzmtTabiQ43/view?usp=sharing PDF]]
−
* Slides: Miller Op-Amp [[https://drive.google.com/file/d/1ARDhJZ5SXZ9aMOgDCBVHqwkQAiG0FLsn/view?usp=sharing PDF]]
+
* Old Slides: Miller Op-Amp [[https://drive.google.com/file/d/1ARDhJZ5SXZ9aMOgDCBVHqwkQAiG0FLsn/view?usp=sharing PDF]]
−
* Videos: [https://drive.google.com/file/d/1XRNRW5x2GmhDsvfyZ-iOt5JvisZaJ-bl/view?usp=sharing Part 1] [https://drive.google.com/file/d/1zOlnA7GNCBQdeKf0cumAQtAe31QDAqoE/view?usp=sharing Part 2]
+
* Old Videos: [https://drive.google.com/file/d/1XRNRW5x2GmhDsvfyZ-iOt5JvisZaJ-bl/view?usp=sharing Part 1] [https://drive.google.com/file/d/1zOlnA7GNCBQdeKf0cumAQtAe31QDAqoE/view?usp=sharing Part 2]
 
|
 
|
−
* Lab 09: Differential Amplifier
+
* [https://drive.google.com/file/d/1-VrmIs0ES5JweacSGyhpaBt4CGYGeR_r/view?usp=sharing Lab 08]: Differential Amplifier
 
|-
 
|-
 
| style="text-align:center;" | 10
 
| style="text-align:center;" | 10
 
|
 
|
−
''May 6-10''
+
''May 17-22''
 
* Folded Cascode Operational Transconductance Amplifiers
 
* Folded Cascode Operational Transconductance Amplifiers
 
|  
 
|  
Line 202: Line 209:
 
* Explain how to design a folded cascode OTA.
 
* Explain how to design a folded cascode OTA.
 
|  
 
|  
−
* Slides: Folded Cascode [[https://drive.google.com/file/d/1Tg0ZyYzh-rQPGdOqmonEXNXNYPkhJ-aW/view?usp=sharing PDF]]
+
* Old Slides: Folded Cascode [[https://drive.google.com/file/d/1Tg0ZyYzh-rQPGdOqmonEXNXNYPkhJ-aW/view?usp=sharing PDF]]
 
|
 
|
−
* Lab 10: Design Problem
+
* [https://drive.google.com/file/d/1SBCZR9B-MiPr_4xueQsOGuSPd9tU7Jdp/view?usp=sharing Design Project]
 
|-
 
|-
−
| style="text-align:center;" colspan="5" | ''May 18: Long Exam 2''
+
| style="text-align:center;" colspan="5" | ''May 29: Long Exam 2''
 
|-
 
|-
 
|}
 
|}
 +
 +
== Announcements ==
 +
Feb 19: Read scaling and MOS switch for Wednesday's (Feb 21) asynch activity. We will have face-to-face discussion on Friday (Feb 23)
 +
 +
Feb 16: Check instructions in UVLe for today's activity
 +
  
 
== Grade distribution ==
 
== Grade distribution ==

Latest revision as of 09:51, 27 May 2024

  • Introduction to Analog and Digital Integrated Circuit Design
  • Semester Offered: 2nd semester
  • Course Credit: Lecture: 3 units (2 units lecture, 1 unit lab)

Catalog Description

IC Fabrication. CMOS gates. Logical Effort. Interconnect. Memory Elements. MOS Amplifiers. Current Sources. Differential Amplifiers. Operational Transconductance Amplifiers.

Pre-req: EEE 41 or EEE 131. 5h (2 lec, 3 lab) 3 u.

Schedule of Classes

Lecture: WF 10-11 am

Laboratory: M 10am-1 pm OR Th 2:30-5:30

Mode of Delivery

For lecture, it will be a mix of face-to-face, and synchronous and asynchronous remote learning.

For laboratory, it will be face-to-face at Rm 403.

Syllabus

Module Topics Outcomes Resources Activities
Part I: Digital Integrated Circuits
0

Feb 12-16

  • Set class expectations, discuss grading system
  • Introduction to CoE 197U
  • Identify the key characteristics and non-idealities of a CMOS fabrication process.
  • Lab orientation
1

Feb 19-23

  • Analyze how key characteristics and non-idealities change the characteristics of the devices that will be built on it.
  • Lab 01: Introduction to Digital IC Design (MOS Characterization)
2

Feb 26-Mar 1

  • Simplify the analysis of a CMOS inverter using switch-level transistor models.
  • Determine key CMOS inverter metrics and understand their significance in the analysis and design process.
  • Design CMOS static gates
3

Mar 4-8

  • Estimate delays of cascaded logic gates
  • Design multistage networks for optimal speed
  • Slides: Logical Effort [PDF]
  • Lab 03: Static CMOS Gates and Delay Optimization
4

Mar 11-15

  • Identify sources of power and energy consumption in digital circuits
  • Evaluate energy efficient techniques for digital logic using defined metrics
  • Model interconnects as parasitic resistances and capacitances and estimate corresponding delay
  • Slides: Power and Energy [PDF]
  • Slides: Interconnects [PDF]
  • Lab 04: Considerations in Digital Design
5

Mar 18-22

  • Enumerate and distinguish different memory element classifications
  • Identify timing parameters relevant to memory elements and their effects on sequential circuit timing
  • Design and characterize basic memory elements
  • Slides: Memory [PDF]
  • Slides: Timing [PDF]
  • Slides: Optional materials [PDF]
  • Video: Module discussion [Link]
  • 2019 Exam: [PDF]
March 23: Long Exam 1
Part II: Analog Integrated Circuits
6

Apr 12-19

  • MOS Amplifiers: DC and AC Analysis
  • Revisit transistor models used for analog circuit design.
  • Identify the limitations of the square-law model.
  • Learn the model-based design methodology.
  • Determine the DC operating point of MOS amplifiers.
  • Extract the MOS small-signal parameters depending on the DC operating point.
  • Analyze MOS amplifiers in the AC and DC domain.
  • Derive the two-port network representation of MOS amplifiers.
  • Identify the appropriate application of a MOS amplifier topology based on its two-port parameters.
  • Slides: Transistor Models [PDF]
  • Slides: Model-Based Design [PDF]
  • Slides: DC and AC Analysis of Single-Stage Amplifiers [PDF]
  • Old Slides: DC and AC Analysis [PDF]
  • Old Videos: Part 1 Part 2
  • Lab 05: Introduction to Analog IC Design (MOS Transistor Characterization)
7

Apr 22-26

  • MOS Amplifiers: Frequency Response
  • Analyze MOS amplifiers in the frequency domain.
  • Sketch the Bode plots of the transfer function.
  • Estimate the dominant pole using ZVTCA.
  • Slides: Frequency Response Part 1 [PDF]
  • Zoom recording: [LINK]
  • Slides: Frequency Response Part 2 [PDF]
  • Old Slides: Frequency Response [PDF]
  • Old Videos: Part 1 Part 2 Part 3
  • Lab 06: Common-Source Amplifier with Resistive Load
8

May 3-8

  • Current Sources
  • High-Swing Current Sources
  • Understand ideal and real sources
  • Analyze MOS simple current mirror
  • Analyze High-swing current sources
9

May 10-15

  • Understand differential circuits
  • Analyze MOS differential pairs
  • Understand operational amplifier operation
  • Analyze Miller Operational Amplifiers
  • Old Slides: MOS Differential Pairs [PDF]
  • Old Slides: Miller Op-Amp [PDF]
  • Old Videos: Part 1 Part 2
  • Lab 08: Differential Amplifier
10

May 17-22

  • Folded Cascode Operational Transconductance Amplifiers
  • Identify the different stages in a folded cascode OTA.
  • Determine the components and/or parameters that affect the DC operating point of a folded cascode OTA.
  • Explain how to design a folded cascode OTA.
  • Old Slides: Folded Cascode [PDF]
May 29: Long Exam 2

Announcements

Feb 19: Read scaling and MOS switch for Wednesday's (Feb 21) asynch activity. We will have face-to-face discussion on Friday (Feb 23)

Feb 16: Check instructions in UVLe for today's activity


Grade distribution

60% Laboratory

30% Long Exams

10% Lecture Class Participation

References

  • Rabaey, Chandrakasan, Nikolic, Digital Integrated Circuits, 2ed., Pearson 2002.
  • Gray, Hurst, Lewis, Meyer, Analysis & Design of Analog Integrated Circuits, Wiley 2001.
  • Johns, Martin, Analog Integrated Circuit Design, Wiley 1997.
  • Design of Analog CMOS Integrated Circuits, Behzad Razavi, McGraw-Hill, 2000.
  • R. Jacob Baker, Circuit Design, Layout,and Simulation, 4ed., IEEE Press 2019.
Retrieved from "https://classes.up-microlab.org/index.php?title=CoE_197U_S2_AY_2023-2024&oldid=4245"