CoE 197U CMOS Inverter

To understand the analysis and design of digital circuits, we will look at its fundamental element -- the digital gate. We will start with the simplest digital gate, the inverter, and look at the basic functionality, static metrics, delay, power, and energy characteristics of CMOS inverters.

The Inverter Voltage Transfer Characteristics (VTC)

The functionality of the inverter can be captured by looking at the output voltage as we change the input voltage, or the voltage-transfer characteristic (VTC).

The Ideal Inverter VTC

Let us define an ideal inverter, where:

$v_{O}={\begin{cases}V_{H},&{\text{if }}v_{I}<V_{REF}\\V_{L},&{\text{if }}v_{I}\geq V_{REF}\end{cases}}$

(1)

Where $V_{H}$ is logic 1 voltage level, and in general may or may not be equal to the positive supply voltage, $V_{+}$, and $V_{L}$ is logic 0 voltage level, and in general may or may not be equal to the negative supply voltage, $V_{-}$. The VTC of this ideal inverter, as well as the standard inverter circuit symbol, is shown in Fig. 1.

Figure 1: The ideal inverter voltage transfer characteristic (VTC).

Inverter Implementations

One implementation of the inverter is to use a single NMOS transistor and a resistor, as shown in Fig. 2. Using our switch model for the NMOS transistor, we can see that when the input is low or at logic 0, the output is pulled up to $V_{DD}$ since the switch is open. When the input voltage is equal to $V_{DD}>V_{TH}$, the switch is closed and the output is pulled down close to ground. For a finite on switch resistance, $R_{ON}$, the output voltage becomes:

$v_{O}={\frac {R_{ON}}{R_{ON}+R}}\cdot V_{DD}$

(2)

Note that a finite $R_{ON}$ will degrade (increase) low output voltage or logic 0 level. Additionally, the when the output of the NMOS inverter is low, there is a non-zero current flowing through the resistor, resulting in static power consumption, or power consumed from the supply even when there is no switching activity present in the circuit.

Figure 2: The NMOS inverter.

Figure 3: The CMOS inverter.

Another implementation of the inverter is to use an NMOS and a PMOS transistor. This complementary (CMOS) configuration turns on only one switch at a time since the gates of the two transistors are connected to each other. Thus, an input voltage of $V_{DD}>V_{TH}$ will turn on (close) the NMOS switch, and turn off (open) the PMOS switch since the gate-to-source voltage of the PMOS transistor is zero, pulling the inverter output down to ground. When the input voltage is ground or logic 0, the NMOS switch is open and the PMOS is closed, pulling the output up to $V_{DD}$.

Note that due to the complementary function of the CMOS inverter, there is no static current flowing when the output is either at logic 0 or logic 1. However, current will flow during the transition from 0$\rightarrow$1 or 1$\rightarrow$0.

We can derive the VTC of any inverter by determining the regions of operation of each transistor as we vary the input voltage. Fig. 4 shows the VTC of the CMOS inverter with the corresponding regions of operation, which are dependent on the input and output voltages. Note that:

• $v_{GS,{\text{n}}}=v_{I}$
• $v_{GS,{\text{p}}}=V_{DD}-v_{I}$
• $v_{DS,{\text{n}}}=v_{O}$
• $v_{DS,{\text{p}}}=V_{DD}-v_{O}$.

Figure 4: The CMOS inverter voltage transfer characteristic (VTC).

Static Design Metrics

The general form of the inverter voltage transfer characteristic is shown in Fig. 5. We can define several metrics to enable us to determine how close the real VTC is to the ideal VTC.

Figure 5: The non-ideal inverter voltage transfer characteristic (VTC).

Figure 6: Noise margin definitions.

Let us define the following basic inverter VTC features:

• $V_{OH}$ is the nominal output high or logic 1 output of the inverter, and is seen at the output when $V_{OL}$ or logic 0 is placed at the input of the inverter.
• $V_{OL}$ is the nominal output low or logic 0 output of the inverter, and is seen at the output when $V_{OH}$ or logic 1 is placed at the input of the inverter.
• If we connect the output of the inverter to its input, then we would expect the voltage to settle at the point where $v_{O}=v_{I}=V_{M}$, or the midpoint voltage. Graphically, this can be determined by drawing a 45-degree line on the VTC curve, as shown in Fig. 5.

In the ideal inverter VTC in Fig. 1, we see that we have two flat regions (zero gain) and a vertical region (infinite gain). However, in a non-ideal VTC, the zero gain regions degrade into low gain regions where the absolute value of the slope is typically less than 1, and a high-gain region where the absolute value of the slope is greater than 1. The boundaries between the high- and low-gain regions are marked by the points where the absolute value of the slope of the VTC is equal to 1.

The two points with a slope of $-1$ are shown in Fig. 5, where $V_{IL}$ is the highest input voltage the inverter will still consider as a low voltage. Anything above this places the inverter in the high-gain region of the VTC, making it sensitive to noise and interference. Similarly, $V_{IH}$ is the lowest input voltage the inverter will still consider as a high voltage.

Noise in Digital Circuits

One of the main advantages of digital circuits over analog circuits is its relatively good noise immunity. In a binary digital logic system, we reduce the amount of information carried by a digital signal to just 1 bit. This then increases the digital circuit's robustness to interference from nearby signals, or from inherent device noise. The zero-gain regions of the ideal inverter VTC are ideal at the points near $V_{H}$ and $V_{L}$ since any disturbance or noise added to the input voltage would just be ignored by the inverter, i.e. the output voltage will not change.

Noise Margins

To quantify this robustness to noise and interference, we define the following metrics as illustrated in Fig. 6:

• $NM_{H}=V_{OH}-V_{IH}$ is the noise margin at the high output level, and is the maximum noise that can reduce the input high or logic 1 level to the point where the inverter might not recognize it as a high level anymore.
• $NM_{L}=V_{IL}-V_{OL}$ is the noise margin at the low output level, and is the maximum noise that can increase the input low or logic 0 level to the point where the inverter might not recognize it as a low level anymore.

Note that input signals between $V_{IL}$ and $V_{IH}$ are considered to be in the indeterminate or undefined region, where because of the high gain, small variations in the input could result in large output variations, possibly leading to erroneous inverter outputs.

The Regenerative Property of Inverters

It is desirable to have a VTC with two low-gain regions, at the nominal input and output voltages, that are separated by a high-gain region. An inverter with this type of VTC is called a regenerative inverter. This means that if a signal is degraded by noise, leaving it in the indeterminate or undefined zone, then by passing this signal into a chain of inverters, the signal will eventually approach one of the nominal voltage levels, as seen in Fig. 7.

Figure 7: The regenerative property of cascaded inverters.

Inverter Delay

Aside from the static metrics, we also have the inverter dynamic characteristics, or what happens to the inverter when the input changes from high to low, or low to high. Specifically, we are interested in the time it takes for the output to settle to its correct value once the input has changed.

Figure 8: Logic delay definitions .

To easily compare delays, we use the standard delay definitions in Fig. 8.

• The rise time, $t_{r}$, is defined as the time it takes for a 0$\rightarrow$1 transition to go from 10% to 90% of its voltage swing.
• The fall time, $t_{f}$, is defined as the time it takes for a 1$\rightarrow$0 transition to go from 90% to 10% of its voltage swing.
• The propagation delay, $t_{p}$ is defined as the time interval between the time the input reaches 50% of its voltage swing to the time the output reaches 50% of its voltage swing. Since the propagation delay does not have to be the same for a 0$\rightarrow$1 and a 1$\rightarrow$0 output transition, we can evaluate the propagation delay for each of these cases:
  • The propagation delay, high-to-low, $t_{pHL}$, is the propagation delay when the output transitions from high to low.
  • The propagation delay, low-to-high, $t_{pLH}$, is the propagation delay when the output transitions from low to high.

A Simple CMOS Inverter Delay Model

Let us try to estimate the delay of an inverter. First, we recognize that in a purely CMOS digital system, an inverter will drive another CMOS gate, and in this case, let us simplify it to just an inverter. The inverter input impedance is capacitive since we are looking into the gate of both the NMOS and PMOS transistors. Secondly, this output capacitance will be charged by the PMOS transistor when the output transitions from low to high, and it will be discharged by the NMOS when the output goes from high to low. Thus, we can model each transition separately.

For the low-to-high transition, we can model the CMOS inverter as ON resistance of the PMOS charging the load capacitance as seen in Fig. 9. The high-to-low transition can be modeled in a similar fashion, as shown in Fig. 10.

Figure 9: The CMOS inverter RC low-to-high delay model.

Figure 10: The CMOS inverter RC high-to-low delay model.

For the simple RC model, we can easily calculate the output low-to-high step response as:

$v_{O}\left(t\right)=V_{DD}\cdot \left(1-e^{-{\frac {t}{\tau _{p}}}}\right)$

(3)

Where $\tau _{p}=R_{ON{\text{,p}}}C_{L}$. Thus, the propagation delay is the time it takes for the output to reach ${\tfrac {V_{DD}}{2}}$ is:

$t_{pLH}=\ln 2\cdot \tau _{p}=0.69\cdot \tau _{p}$

(4)

Similarly, the propagation delay from high to low is:

$t_{pHL}=\ln 2\cdot \tau _{n}=0.69\cdot \tau _{n}$

(5)

Where $\tau _{n}=R_{ON{\text{,n}}}C_{L}$.

Since the inverter propagation delay is very much dependent on the load capacitance, it is convenient to define a standard capacitance load so we can compare inverters not only of different topologies, but also across different technologies. One convenient way is to get the delay of an inverter with a fan-out of 4 (FO4), or an inverter driving 4 other identical inverters as shown in Fig. 11. Thus, the FO4 inverter delay uses $C_{L}=4\cdot C_{in}$, where $C_{in}$ is the input capacitance of the inverter.

Figure 11: The inverter FO4 delay.