- Introduction to Analog and Digital Integrated Circuit Design
- Semester Offered: 2nd semester
- Course Credit: Lecture: 3 units (2 units lecture, 1 unit lab)
Catalog Description
IC Fabrication. CMOS gates. Logical Effort. Interconnect. Memory Elements. MOS Amplifiers. Current Sources. Differential Amplifiers. Operational Transconductance Amplifiers.
Pre-req: EEE 41 or EEE 131. 5h (2 lec, 3 lab) 3 u.
Syllabus
| Module
|
Topics
|
Outcomes
|
Resources
|
Activities
|
| Part I: Digital Integrated Circuits
|
| 0
|
Feb 13-18
|
- Set class expectations, discuss grading system
- Introduction to CoE 197U
|
|
|
| 1
|
Feb 20-25
|
- Identify the key characteristics and non-idealities of a CMOS fabrication process.
- Analyze how these key characteristics and non-idealities change the characteristics of the devices that will be built on it.
|
|
- CoE197U-A1.1: IC Fabrication and Scaling
- Lab 01: Introduction to Digital IC Design (MOS Characterization)
|
| 2
|
Mar 6-11
|
- Simplify the analysis of a CMOS inverter using switch-level transistor models.
- Determine key CMOS inverter metrics and understand their significance in the analysis and design process.
|
- Slides: MOS [PDF]
- Slides: CMOS Inverter [PDF]
- Recording: Module Discussion [Video]
|
|
| 3
|
Mar 13-18
|
- Design CMOS static gates
- Estimate delays of cascaded logic gates
- Design multistage networks for optimal speed
|
- Slides: CMOS Gates [PDF]
- Slides: Logical Effort [PDF]
- Additional Slides: LE Example [PDF]
|
- HW Module 3 HW (final extension May 5)
- Lab 03: Static CMOS Gates
|
| 4
|
Mar 20-25
|
- Identify sources of power and energy consumption in digital circuits
- Evaluate energy efficient techniques for digital logic using defined metrics
- Model interconnects as parasitic resistances and capacitances and estimate corresponding delay
|
- Slides: Power and Energy [PDF]
- Slides: Interconnects [PDF]
|
- Lab 04: Delay Optimization and Considerations in Digital Design
|
| 5
|
Mar 20-25
|
- Enumerate and distinguish different memory element classifications
- Identify timing parameters relevant to memory elements and their effects on sequential circuit timing
- Design and characterize basic memory elements
|
- Slides: Memory [PDF]
- Slides: Timing [PDF]
- Slides: Optional materials [PDF]
- Video: Module discussion [Link]
- 2019 Exam: [PDF]
|
|
| Part II: Analog Integrated Circuits
|
| 6
|
Apr 17-22
- MOS Amplifiers: DC and AC Analysis
|
- Determine the DC operating point of MOS amplifiers.
- Extract the MOS small-signal parameters depending on the DC operating point.
- Analyze MOS amplifiers in the AC and DC domain.
- Derive the two-port network representation of MOS amplifiers.
- Identify the appropriate application of a MOS amplifier topology based on its two-port parameters.
|
|
- Lab 05: Introduction to Analog IC Design (MOS Characterization)
|
| 7
|
Apr 24-29
- MOS Amplifiers: Frequency Response
|
- Analyze MOS amplifiers in the frequency domain.
- Sketch the Bode plots of the transfer function.
- Estimate the dominant pole using ZVTCA.
|
|
- Lab 06: Common-Source Amplifier with Resistive Load
|
| 8
|
May 8-13
- Current Sources
- High-Swing Current Sources
|
- Understand ideal and real sources
- Analyze MOS simple current mirror
- Analyze High-swing current sources
|
|
|
| 9
|
May 15-20
|
- Understand differential circuits
- Analyze MOS differential pairs
- Understand operational amplifier operation
- Analyze Miller Operational Amplifiers
|
|
- Lab 08: Differential Amplifier
|
| 10
|
May 22-27
- Folded Cascode Operational Transconductance Amplifiers
|
- Identify the different stages in a folded cascode OTA.
- Determine the components and/or parameters that affect the DC operating point of a folded cascode OTA.
- Explain how to design a folded cascode OTA.
|
- Slides: Folded Cascode [PDF]
|
|
References
- Rabaey, Chandrakasan, Nikolic, Digital Integrated Circuits, 2ed., Pearson 2002.
- Gray, Hurst, Lewis, Meyer, Analysis & Design of Analog Integrated Circuits, Wiley 2001.
- Johns, Martin, Analog Integrated Circuit Design, Wiley 1997.
- Design of Analog CMOS Integrated Circuits, Behzad Razavi, McGraw-Hill, 2000.
- R. Jacob Baker, Circuit Design, Layout,and Simulation, 4ed., IEEE Press 2019.
