Difference between revisions of "CoE 197U S2 AY 2023-2024"

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* Analyze how these key characteristics and non-idealities change the characteristics of the devices that will be built on it.
 
* Analyze how these key characteristics and non-idealities change the characteristics of the devices that will be built on it.
 
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* Video: Silicon Run I (1996) [https://www.youtube.com/watch?v=3XTWXRj24GM Youtube link]
 
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* Lab orientation
 
* Lab orientation
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''Feb 19-23''
 
''Feb 19-23''
 
* [[CoE 197U Scaling | Scaling]]
 
* [[CoE 197U Scaling | Scaling]]
 +
* [[CoE 197U The MOS Transistor | The MOS Transistor]]
 +
* [[CoE 197U The MOS Switch | The MOS Switch]]
 
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* Identify the key characteristics and non-idealities of a CMOS fabrication process.
 
* Identify the key characteristics and non-idealities of a CMOS fabrication process.
 
* Analyze how these key characteristics and non-idealities change the characteristics of the devices that will be built on it.
 
* Analyze how these key characteristics and non-idealities change the characteristics of the devices that will be built on it.
 
|  
 
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−
* Video: Silicon Run I (1996) [https://www.youtube.com/watch?v=3XTWXRj24GM Youtube link]
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* Slides: MOS
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* Paolo Gargini's [https://www.dropbox.com/s/6eskh6bwdcuzpsa/1507_11_Paolo%20Overview_Out.pdf presentation] from the 2015 [http://www.itrs2.net/ International Technology Roadmap for Semiconductors] (ITRS) Summer Meeting.
 
 
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* [[CoE197U-A1.1]]: IC Fabrication and Scaling
 
* [[CoE197U-A1.1]]: IC Fabrication and Scaling
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''Feb 26-Mar 1''
 
''Feb 26-Mar 1''
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* [[CoE 197U The MOS Transistor | The MOS Transistor]]
 
−
* [[CoE 197U The MOS Switch | The MOS Switch]]
 
 
* [[CoE 197U CMOS Inverter | The CMOS Inverter]]
 
* [[CoE 197U CMOS Inverter | The CMOS Inverter]]
 +
* [[ CoE 197U CMOS Gates | Static CMOS Gates ]]
 
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* Simplify the analysis of a CMOS inverter using switch-level transistor models.
 
* Simplify the analysis of a CMOS inverter using switch-level transistor models.
 
* Determine key CMOS inverter metrics and understand their significance in the analysis and design process.
 
* Determine key CMOS inverter metrics and understand their significance in the analysis and design process.
 +
* Design CMOS static gates
 
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* Slides: MOS [[https://drive.google.com/file/d/1H-aBeApfPlgFNqAMoMqIDZSbyDmwHFPf/view?usp=sharing PDF]]
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* Slides: CMOS Inverter
−
* Slides: CMOS Inverter [[https://drive.google.com/file/d/1H4Dt_YkLFLWvAVurp7ZxcXbJAPw6frR5/view?usp=sharing PDF]]
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* Slides: CMOS Gates
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* Recording: Module Discussion [[https://drive.google.com/file/d/1H5yoNWBSQfp_TSfS6voFygigZTX6G97F/view?usp=sharing Video]]
 
 
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* [https://drive.google.com/file/d/18UYFxIaRGhsmvG85DYrZjySjsFcbuUlm/view?usp=sharing Lab 02]: CMOS Inverter
 
* [https://drive.google.com/file/d/18UYFxIaRGhsmvG85DYrZjySjsFcbuUlm/view?usp=sharing Lab 02]: CMOS Inverter
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''Mar 4-8''
 
''Mar 4-8''
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* [[ CoE 197U CMOS Gates | Static CMOS Gates ]]
 
 
* [[ CoE 197U Logical Effort | Logical Effort and Delay ]]
 
* [[ CoE 197U Logical Effort | Logical Effort and Delay ]]
 
|  
 
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−
* Design CMOS static gates
 
 
* Estimate delays of cascaded logic gates
 
* Estimate delays of cascaded logic gates
 
* Design multistage networks for optimal speed
 
* Design multistage networks for optimal speed
 
|  
 
|  
−
* Slides: CMOS Gates [[https://drive.google.com/file/d/10McCC1megDnllbIMj7rdtBlyZB84QVBh/view?usp=sharing PDF]]
 
 
* Slides: Logical Effort [[https://drive.google.com/file/d/10dGqE_NolixkYaL7aUWMlwPaIILprEFg/view?usp=sharing PDF]]
 
* Slides: Logical Effort [[https://drive.google.com/file/d/10dGqE_NolixkYaL7aUWMlwPaIILprEFg/view?usp=sharing PDF]]
 
* Additional Slides: LE Example [[https://drive.google.com/file/d/1IvgU-3yIFlPBbj0PAdfdnyrPYkas3qnf/view?usp=sharing PDF]]
 
* Additional Slides: LE Example [[https://drive.google.com/file/d/1IvgU-3yIFlPBbj0PAdfdnyrPYkas3qnf/view?usp=sharing PDF]]
 
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<!-- * [[CoE197U-A3.1]]: Logical Effort -->
 
<!-- * [[CoE197U-A3.1]]: Logical Effort -->
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* [https://drive.google.com/file/d/1IgdNWWsXWqQegJP914KjZ7m4zVZ5LEQo/view?usp=sharing HW] Module 3 HW (final extension May 5)
 
 
* [https://drive.google.com/file/d/18_k97CdiAwOJ8LjWhrWcoZDJZjG6fyq7/view?usp=sharing Lab 03]: Static CMOS Gates
 
* [https://drive.google.com/file/d/18_k97CdiAwOJ8LjWhrWcoZDJZjG6fyq7/view?usp=sharing Lab 03]: Static CMOS Gates
 
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''Mar 11-15''
 
''Mar 11-15''
 
* [[ CoE 197U Power and Energy | Power and Energy ]]
 
* [[ CoE 197U Power and Energy | Power and Energy ]]
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* Optional: [[ CoE 197U Interconnects | Interconnects ]]
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* [[ CoE 197U Interconnects | Interconnects ]]
 
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* Identify sources of power and energy consumption in digital circuits
 
* Identify sources of power and energy consumption in digital circuits

Revision as of 11:11, 11 February 2024

  • Introduction to Analog and Digital Integrated Circuit Design
  • Semester Offered: 2nd semester
  • Course Credit: Lecture: 3 units (2 units lecture, 1 unit lab)

Catalog Description

IC Fabrication. CMOS gates. Logical Effort. Interconnect. Memory Elements. MOS Amplifiers. Current Sources. Differential Amplifiers. Operational Transconductance Amplifiers.

Pre-req: EEE 41 or EEE 131. 5h (2 lec, 3 lab) 3 u.

Schedule of Classes

Lecture: WF 10-11 am

Laboratory: M 10am-1 pm OR Th 2:30-5:30

Mode of Delivery

For lecture, it will be a mix of face-to-face, and synchronous and asynchronous remote learning.

For laboratory, it will be face-to-face at Rm 403.

Syllabus

Module Topics Outcomes Resources Activities
Part I: Digital Integrated Circuits
0

Feb 12-16

  • Set class expectations, discuss grading system
  • Introduction to CoE 197U
  • Identify the key characteristics and non-idealities of a CMOS fabrication process.
  • Analyze how these key characteristics and non-idealities change the characteristics of the devices that will be built on it.
  • Lab orientation
1

Feb 19-23

  • Identify the key characteristics and non-idealities of a CMOS fabrication process.
  • Analyze how these key characteristics and non-idealities change the characteristics of the devices that will be built on it.
  • Slides: MOS
  • CoE197U-A1.1: IC Fabrication and Scaling
  • Lab 01: Introduction to Digital IC Design (MOS Characterization)
2

Feb 26-Mar 1

  • Simplify the analysis of a CMOS inverter using switch-level transistor models.
  • Determine key CMOS inverter metrics and understand their significance in the analysis and design process.
  • Design CMOS static gates
  • Slides: CMOS Inverter
  • Slides: CMOS Gates
3

Mar 4-8

  • Estimate delays of cascaded logic gates
  • Design multistage networks for optimal speed
  • Slides: Logical Effort [PDF]
  • Additional Slides: LE Example [PDF]
4

Mar 11-15

  • Identify sources of power and energy consumption in digital circuits
  • Evaluate energy efficient techniques for digital logic using defined metrics
  • Model interconnects as parasitic resistances and capacitances and estimate corresponding delay
  • Slides: Power and Energy [PDF]
  • Slides: Interconnects [PDF]
  • Lab 04: Delay Optimization and Considerations in Digital Design
5

Mar 18-22

  • Enumerate and distinguish different memory element classifications
  • Identify timing parameters relevant to memory elements and their effects on sequential circuit timing
  • Design and characterize basic memory elements
  • Slides: Memory [PDF]
  • Slides: Timing [PDF]
  • Slides: Optional materials [PDF]
  • Video: Module discussion [Link]
  • 2019 Exam: [PDF]
March 23: Long Exam 1
Part II: Analog Integrated Circuits
6

Apr 8-12

  • MOS Amplifiers: DC and AC Analysis
  • Determine the DC operating point of MOS amplifiers.
  • Extract the MOS small-signal parameters depending on the DC operating point.
  • Analyze MOS amplifiers in the AC and DC domain.
  • Derive the two-port network representation of MOS amplifiers.
  • Identify the appropriate application of a MOS amplifier topology based on its two-port parameters.
  • Lab 06: Introduction to Analog IC Design (MOS Characterization)
7

Apr 15-19

  • MOS Amplifiers: Frequency Response
  • Analyze MOS amplifiers in the frequency domain.
  • Sketch the Bode plots of the transfer function.
  • Estimate the dominant pole using ZVTCA.
  • Lab 07: Common-Source Amplifier with Resistive Load
8

Apr 22-26

  • Current Sources
  • High-Swing Current Sources
  • Understand ideal and real sources
  • Analyze MOS simple current mirror
  • Analyze High-swing current sources
  • Lab 08: Current Sources
9

Apr 29-May 3

  • Understand differential circuits
  • Analyze MOS differential pairs
  • Understand operational amplifier operation
  • Analyze Miller Operational Amplifiers
  • Lab 09: Differential Amplifier
10

May 6-10

  • Folded Cascode Operational Transconductance Amplifiers
  • Identify the different stages in a folded cascode OTA.
  • Determine the components and/or parameters that affect the DC operating point of a folded cascode OTA.
  • Explain how to design a folded cascode OTA.
  • Slides: Folded Cascode [PDF]
  • Lab 10: Design Problem
May 18: Long Exam 2

Grade distribution

60% Laboratory

30% Long Exams

10% Lecture Class Participation

References

  • Rabaey, Chandrakasan, Nikolic, Digital Integrated Circuits, 2ed., Pearson 2002.
  • Gray, Hurst, Lewis, Meyer, Analysis & Design of Analog Integrated Circuits, Wiley 2001.
  • Johns, Martin, Analog Integrated Circuit Design, Wiley 1997.
  • Design of Analog CMOS Integrated Circuits, Behzad Razavi, McGraw-Hill, 2000.
  • R. Jacob Baker, Circuit Design, Layout,and Simulation, 4ed., IEEE Press 2019.
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