Difference between revisions of "CoE 197U S2 AY 2021-2022"
Jump to navigation
Jump to search
Line 56: | Line 56: | ||
* Design multistage networks for optimal speed | * Design multistage networks for optimal speed | ||
| | | | ||
− | * Slides: CMOS Gates [https://drive.google.com/file/d/ | + | * Slides: CMOS Gates [https://drive.google.com/file/d/10McCC1megDnllbIMj7rdtBlyZB84QVBh/view?usp=sharing PDF] |
− | * Slides: Logical Effort [https://drive.google.com/file/d/ | + | * Slides: Logical Effort [https://drive.google.com/file/d/10dGqE_NolixkYaL7aUWMlwPaIILprEFg/view?usp=sharing PDF] |
| | | | ||
* [[CoE197U-A3.1]]: Logical Effort | * [[CoE197U-A3.1]]: Logical Effort |
Latest revision as of 08:13, 27 June 2022
- Introduction to Analog and Digital Integrated Circuit Design
- Semester Offered: 2nd semester
- Course Credit: Lecture: 3 units (2 units lecture, 1 unit lab)
Catalog Description
IC Fabrication. CMOS gates. Logical Effort. Interconnect. Memory Elements. MOS Amplifiers. Current Sources. Differential Amplifiers. Operational Transconductance Amplifiers. Pre-req: EEE 41 or EEE 131. 5h (2 lec, 3 lab) 3 u.
Syllabus
Module | Topics | Outcomes | Resources | Activities |
---|---|---|---|---|
Part I: Digital Integrated Circuits | ||||
1 |
|
|
| |
2 |
|
| ||
3 |
|
| ||
4 |
|
| ||
5 |
|
| ||
Part II: Analog Integrated Circuits | ||||
6 |
|
|
| |
7 |
|
|
| |
8 |
|
|
| |
9 |
|
| ||
10 |
|
|
|
|
References
- Rabaey, Chandrakasan, Nikolic, Digital Integrated Circuits, 2ed., Pearson 2002.
- Gray, Hurst, Lewis, Meyer, Analysis & Design of Analog Integrated Circuits, Wiley 2001.
- Johns, Martin, Analog Integrated Circuit Design, Wiley 1997.
- Design of Analog CMOS Integrated Circuits, Behzad Razavi, McGraw-Hill, 2000.
- R. Jacob Baker, Circuit Design, Layout,and Simulation, 4ed., IEEE Press 2019.