Difference between revisions of "CoE 197U S2 AY 2021-2022"
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* [[CoE 197U The MOS Transistor | The MOS Transistor]] | * [[CoE 197U The MOS Transistor | The MOS Transistor]] | ||
* [[CoE 197U The MOS Switch | The MOS Switch]] | * [[CoE 197U The MOS Switch | The MOS Switch]] | ||
− | * [[CoE 197U | + | * [[CoE 197U CMOS Inverter | The CMOS Inverter]] |
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* Simplify the analysis of a CMOS inverter using switch-level transistor models. | * Simplify the analysis of a CMOS inverter using switch-level transistor models. | ||
* Determine key CMOS inverter metrics and understand their significance in the analysis and design process. | * Determine key CMOS inverter metrics and understand their significance in the analysis and design process. | ||
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+ | * Slides: MOS [https://drive.google.com/file/d/1dfJrPqlxJoZ4AhReXXWi5k8-6cSgZvSz/view?usp=sharing PDF] | ||
+ | * Slides: CMOS Inverter [https://drive.google.com/file/d/1dcLgThoGYp5P-mDGirC0-dJNbvaj3MLl/view?usp=sharing PDF] | ||
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* [https://uvle.upd.edu.ph/mod/resource/view.php?id=144093 Lab 02]: The MOSFET Switch and The Inverter | * [https://uvle.upd.edu.ph/mod/resource/view.php?id=144093 Lab 02]: The MOSFET Switch and The Inverter | ||
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* Design multistage networks for optimal speed | * Design multistage networks for optimal speed | ||
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− | * Slides: CMOS Gates [https://drive.google.com/file/d/ | + | * Slides: CMOS Gates [https://drive.google.com/file/d/10McCC1megDnllbIMj7rdtBlyZB84QVBh/view?usp=sharing PDF] |
− | * Slides: Logical Effort [https://drive.google.com/file/d/ | + | * Slides: Logical Effort [https://drive.google.com/file/d/10dGqE_NolixkYaL7aUWMlwPaIILprEFg/view?usp=sharing PDF] |
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* [[CoE197U-A3.1]]: Logical Effort | * [[CoE197U-A3.1]]: Logical Effort | ||
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* Model interconnects as parasitic resistances and capacitances and estimate corresponding delay | * Model interconnects as parasitic resistances and capacitances and estimate corresponding delay | ||
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− | * Slides: Power and Energy [https://drive.google.com/file/d/ | + | * Slides: Power and Energy [https://drive.google.com/file/d/1gbC7LNLFHcncVy0QKoAVykm5zr6tY8D5/view?usp=sharing PDF] |
* Slides: Interconnects [https://drive.google.com/file/d/1Or0KnHb3v0awBcXZHd8CfN2oEP5l3cRj/view?usp=sharing PDF] | * Slides: Interconnects [https://drive.google.com/file/d/1Or0KnHb3v0awBcXZHd8CfN2oEP5l3cRj/view?usp=sharing PDF] | ||
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− | * [https:// | + | * [https://uvle.upd.edu.ph/mod/resource/view.php?id=199635 Lab 04] : Static Logic Gates and Logical Effort |
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| style="text-align:center;" | 5 | | style="text-align:center;" | 5 | ||
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* Design and characterize basic memory elements | * Design and characterize basic memory elements | ||
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− | * Slides: Memory [https://drive.google.com/file/d/ | + | * Slides: Memory [https://drive.google.com/file/d/1h4k-rx-d1iNcbZrvv6cD3GcNqs5GzNIj/view?usp=sharing PDF] |
− | * Slides: Timing [https://drive.google.com/file/d/ | + | * Slides: Timing [https://drive.google.com/file/d/1hA5C63P1zuBascs2_n4ZI_m2XzpEhAQ-/view?usp=sharing PDF] |
− | |||
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* [[CoE197U-A5.1]]: Timing | * [[CoE197U-A5.1]]: Timing | ||
− | * [https:// | + | * [https://uvle.upd.edu.ph/mod/resource/view.php?id=199751 Lab 05] : Power Delay Product and Memory Elements |
|- | |- | ||
| style="text-align:center;" colspan="5" | ''Part II: Analog Integrated Circuits'' | | style="text-align:center;" colspan="5" | ''Part II: Analog Integrated Circuits'' | ||
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* Videos: [https://www.youtube.com/watch?v=4tEYeFiYwWI&list=PL4if6jkKNTz9RgsB4Gq_g374b4oLYOAeH&index=1 Part 1] [https://www.youtube.com/watch?v=lD7ejAl4Ue4&list=PL4if6jkKNTz9RgsB4Gq_g374b4oLYOAeH&index=2 Part 2] | * Videos: [https://www.youtube.com/watch?v=4tEYeFiYwWI&list=PL4if6jkKNTz9RgsB4Gq_g374b4oLYOAeH&index=1 Part 1] [https://www.youtube.com/watch?v=lD7ejAl4Ue4&list=PL4if6jkKNTz9RgsB4Gq_g374b4oLYOAeH&index=2 Part 2] | ||
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+ | * Lab 06: Introduction to Analog Design | ||
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| style="text-align:center;" | 7 | | style="text-align:center;" | 7 | ||
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* Videos: [https://www.youtube.com/watch?v=1AzlCV_AXgg&list=PL4if6jkKNTz9RgsB4Gq_g374b4oLYOAeH&index=3 Part 1] [https://www.youtube.com/watch?v=I3I6CBye0rU&list=PL4if6jkKNTz9RgsB4Gq_g374b4oLYOAeH&index=4 Part 2] [https://www.youtube.com/watch?v=55w6EXRSR1M&list=PL4if6jkKNTz9RgsB4Gq_g374b4oLYOAeH&index=5 Part 3] | * Videos: [https://www.youtube.com/watch?v=1AzlCV_AXgg&list=PL4if6jkKNTz9RgsB4Gq_g374b4oLYOAeH&index=3 Part 1] [https://www.youtube.com/watch?v=I3I6CBye0rU&list=PL4if6jkKNTz9RgsB4Gq_g374b4oLYOAeH&index=4 Part 2] [https://www.youtube.com/watch?v=55w6EXRSR1M&list=PL4if6jkKNTz9RgsB4Gq_g374b4oLYOAeH&index=5 Part 3] | ||
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+ | * Lab 07: CS Amplifier and Frequency Response | ||
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| style="text-align:center;" | 8 | | style="text-align:center;" | 8 | ||
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* Slides: High-Swing Current Sources [https://drive.google.com/file/d/15dsEE2jcVoUNasZmvCOlewN77UxfOieB/view?usp=sharing PDF] | * Slides: High-Swing Current Sources [https://drive.google.com/file/d/15dsEE2jcVoUNasZmvCOlewN77UxfOieB/view?usp=sharing PDF] | ||
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+ | * Lab 08: Current Mirrors and CS Amplifiers with Active Loads | ||
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| style="text-align:center;" | 9 | | style="text-align:center;" | 9 | ||
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* Slides: Miller Op-Amp [https://drive.google.com/file/d/1ARDhJZ5SXZ9aMOgDCBVHqwkQAiG0FLsn/view?usp=sharing PDF] | * Slides: Miller Op-Amp [https://drive.google.com/file/d/1ARDhJZ5SXZ9aMOgDCBVHqwkQAiG0FLsn/view?usp=sharing PDF] | ||
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+ | * Lab 09: Differential Pairs and Two-Stage MOS OTA | ||
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| style="text-align:center;" | 10 | | style="text-align:center;" | 10 | ||
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* Slides: Folded Cascode [https://drive.google.com/file/d/1Tg0ZyYzh-rQPGdOqmonEXNXNYPkhJ-aW/view?usp=sharing PDF] | * Slides: Folded Cascode [https://drive.google.com/file/d/1Tg0ZyYzh-rQPGdOqmonEXNXNYPkhJ-aW/view?usp=sharing PDF] | ||
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+ | * Lab 10: (Project) Design of a Folded Cascode OTA | ||
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|} | |} |
Latest revision as of 08:13, 27 June 2022
- Introduction to Analog and Digital Integrated Circuit Design
- Semester Offered: 2nd semester
- Course Credit: Lecture: 3 units (2 units lecture, 1 unit lab)
Catalog Description
IC Fabrication. CMOS gates. Logical Effort. Interconnect. Memory Elements. MOS Amplifiers. Current Sources. Differential Amplifiers. Operational Transconductance Amplifiers. Pre-req: EEE 41 or EEE 131. 5h (2 lec, 3 lab) 3 u.
Syllabus
Module | Topics | Outcomes | Resources | Activities |
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Part I: Digital Integrated Circuits | ||||
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5 |
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Part II: Analog Integrated Circuits | ||||
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7 |
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8 |
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10 |
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References
- Rabaey, Chandrakasan, Nikolic, Digital Integrated Circuits, 2ed., Pearson 2002.
- Gray, Hurst, Lewis, Meyer, Analysis & Design of Analog Integrated Circuits, Wiley 2001.
- Johns, Martin, Analog Integrated Circuit Design, Wiley 1997.
- Design of Analog CMOS Integrated Circuits, Behzad Razavi, McGraw-Hill, 2000.
- R. Jacob Baker, Circuit Design, Layout,and Simulation, 4ed., IEEE Press 2019.