Difference between revisions of "CoE 197U S2 AY 2021-2022"

From Microlab Classes
Jump to navigation Jump to search
(Created page with "* '''Introduction to Analog and Digital Integrated Circuit Design''' * Semester Offered: 2nd semester * Course Credit: Lecture: 3 units (2 units lecture, 1 unit lab) == Catal...")
 
 
(8 intermediate revisions by 2 users not shown)
Line 31: Line 31:
 
|
 
|
 
* [[CoE197U-A1.1]]: IC Fabrication and Scaling
 
* [[CoE197U-A1.1]]: IC Fabrication and Scaling
−
* [https://drive.google.com/drive/folders/1PFmtjlx1usOf73PzcLBfkcS8VhDb2Pz8?usp=sharing Lab 00]: Introduction to LTspice
+
* [https://uvle.upd.edu.ph/mod/resource/view.php?id=144085 Lab 01]: Introduction to LTSpice
 
|-
 
|-
 
| style="text-align:center;" | 2
 
| style="text-align:center;" | 2
Line 37: Line 37:
 
* [[CoE 197U The MOS Transistor | The MOS Transistor]]
 
* [[CoE 197U The MOS Transistor | The MOS Transistor]]
 
* [[CoE 197U The MOS Switch | The MOS Switch]]
 
* [[CoE 197U The MOS Switch | The MOS Switch]]
−
* [[CoE 197U The CMOS Inverter | The CMOS Inverter]]
+
* [[CoE 197U CMOS Inverter | The CMOS Inverter]]
 
|  
 
|  
 
* Simplify the analysis of a CMOS inverter using switch-level transistor models.
 
* Simplify the analysis of a CMOS inverter using switch-level transistor models.
 
* Determine key CMOS inverter metrics and understand their significance in the analysis and design process.
 
* Determine key CMOS inverter metrics and understand their significance in the analysis and design process.
 
|  
 
|  
 +
* Slides: MOS [https://drive.google.com/file/d/1dfJrPqlxJoZ4AhReXXWi5k8-6cSgZvSz/view?usp=sharing PDF]
 +
* Slides: CMOS Inverter [https://drive.google.com/file/d/1dcLgThoGYp5P-mDGirC0-dJNbvaj3MLl/view?usp=sharing PDF]
 
|
 
|
−
* [https://drive.google.com/drive/folders/1lW3RflMSI0DUz3Rb2CCvzhABtaKJXQRt?usp=sharing Lab 01]: The MOSFET Switch and The Inverter
+
* [https://uvle.upd.edu.ph/mod/resource/view.php?id=144093 Lab 02]: The MOSFET Switch and The Inverter
 
|-
 
|-
 
| style="text-align:center;" | 3
 
| style="text-align:center;" | 3
Line 54: Line 56:
 
* Design multistage networks for optimal speed
 
* Design multistage networks for optimal speed
 
|  
 
|  
−
* Slides: CMOS Gates [https://drive.google.com/file/d/1Ohu6h00q8o3mN6PfKG0_ArZ7F97qvOji/view?usp=sharing PDF]
+
* Slides: CMOS Gates [https://drive.google.com/file/d/10McCC1megDnllbIMj7rdtBlyZB84QVBh/view?usp=sharing PDF]
−
* Slides: Logical Effort [https://drive.google.com/file/d/1OmX857DUfy0X_asE1DKYCIrr9TwwMMvX/view?usp=sharing PDF]
+
* Slides: Logical Effort [https://drive.google.com/file/d/10dGqE_NolixkYaL7aUWMlwPaIILprEFg/view?usp=sharing PDF]
 
|
 
|
 
* [[CoE197U-A3.1]]: Logical Effort
 
* [[CoE197U-A3.1]]: Logical Effort
−
* [https://drive.google.com/drive/folders/1IaQsQZEfm57A4HbENHF_BZrPzi_iwLzQ?usp=sharing Lab 02]: Inverter Characteristics, Ring Oscillator, and Buffers
+
* [https://uvle.upd.edu.ph/mod/resource/view.php?id=144103 Lab 03]: Inverter Characteristics, Ring Oscillator, and Buffers
 
|-
 
|-
 
| style="text-align:center;" | 4
 
| style="text-align:center;" | 4
Line 69: Line 71:
 
* Model interconnects as parasitic resistances and capacitances and estimate corresponding delay
 
* Model interconnects as parasitic resistances and capacitances and estimate corresponding delay
 
|  
 
|  
−
* Slides: Power and Energy [https://drive.google.com/file/d/1OpKOIEaYL6B4tIJ4WBeFDanvIL5H-3RE/view?usp=sharing PDF]
+
* Slides: Power and Energy [https://drive.google.com/file/d/1gbC7LNLFHcncVy0QKoAVykm5zr6tY8D5/view?usp=sharing PDF]
 
* Slides: Interconnects [https://drive.google.com/file/d/1Or0KnHb3v0awBcXZHd8CfN2oEP5l3cRj/view?usp=sharing PDF]
 
* Slides: Interconnects [https://drive.google.com/file/d/1Or0KnHb3v0awBcXZHd8CfN2oEP5l3cRj/view?usp=sharing PDF]
 
|
 
|
−
* [https://drive.google.com/drive/folders/1HtOJQGC0XJqgDrctXn14LnqV1bDGPJv4?usp=sharing Lab 03] : Static Logic Gates and Power-Delay Product
+
* [https://uvle.upd.edu.ph/mod/resource/view.php?id=199635 Lab 04] : Static Logic Gates and Logical Effort
 
|-
 
|-
 
| style="text-align:center;" | 5
 
| style="text-align:center;" | 5
Line 83: Line 85:
 
* Design and characterize basic memory elements
 
* Design and characterize basic memory elements
 
|  
 
|  
−
* Slides: Memory [https://drive.google.com/file/d/1PEUGraNKqPlbqWAljKm1onDU_kUUpk2S/view?usp=sharing PDF]
+
* Slides: Memory [https://drive.google.com/file/d/1h4k-rx-d1iNcbZrvv6cD3GcNqs5GzNIj/view?usp=sharing PDF]
−
* Slides: Timing [https://drive.google.com/file/d/1PEg80QK6j8bnSphWYS9hCrJ-gEOLGuyz/view?usp=sharing PDF]
+
* Slides: Timing [https://drive.google.com/file/d/1hA5C63P1zuBascs2_n4ZI_m2XzpEhAQ-/view?usp=sharing PDF]
−
* Slides: Timing Discussion [https://drive.google.com/file/d/1TvtFsCeWpNUtuFKQrUlx80oc0gTxrYhF/view?usp=sharing PDF]
 
 
|
 
|
 
* [[CoE197U-A5.1]]: Timing
 
* [[CoE197U-A5.1]]: Timing
−
* [https://drive.google.com/drive/folders/1blJPdFy2G7IbzKCFb-2kXf1_vAcJGQ9O?usp=sharing Lab 04] : Basic Memory Devices
+
* [https://uvle.upd.edu.ph/mod/resource/view.php?id=199751 Lab 05] : Power Delay Product and Memory Elements
 
|-
 
|-
 
| style="text-align:center;" colspan="5" | ''Part II: Analog Integrated Circuits''
 
| style="text-align:center;" colspan="5" | ''Part II: Analog Integrated Circuits''
Line 105: Line 106:
 
* Videos: [https://www.youtube.com/watch?v=4tEYeFiYwWI&list=PL4if6jkKNTz9RgsB4Gq_g374b4oLYOAeH&index=1 Part 1] [https://www.youtube.com/watch?v=lD7ejAl4Ue4&list=PL4if6jkKNTz9RgsB4Gq_g374b4oLYOAeH&index=2 Part 2]
 
* Videos: [https://www.youtube.com/watch?v=4tEYeFiYwWI&list=PL4if6jkKNTz9RgsB4Gq_g374b4oLYOAeH&index=1 Part 1] [https://www.youtube.com/watch?v=lD7ejAl4Ue4&list=PL4if6jkKNTz9RgsB4Gq_g374b4oLYOAeH&index=2 Part 2]
 
|
 
|
 +
* Lab 06: Introduction to Analog Design
 
|-
 
|-
 
| style="text-align:center;" | 7
 
| style="text-align:center;" | 7
Line 117: Line 119:
 
* Videos: [https://www.youtube.com/watch?v=1AzlCV_AXgg&list=PL4if6jkKNTz9RgsB4Gq_g374b4oLYOAeH&index=3 Part 1] [https://www.youtube.com/watch?v=I3I6CBye0rU&list=PL4if6jkKNTz9RgsB4Gq_g374b4oLYOAeH&index=4 Part 2] [https://www.youtube.com/watch?v=55w6EXRSR1M&list=PL4if6jkKNTz9RgsB4Gq_g374b4oLYOAeH&index=5 Part 3]
 
* Videos: [https://www.youtube.com/watch?v=1AzlCV_AXgg&list=PL4if6jkKNTz9RgsB4Gq_g374b4oLYOAeH&index=3 Part 1] [https://www.youtube.com/watch?v=I3I6CBye0rU&list=PL4if6jkKNTz9RgsB4Gq_g374b4oLYOAeH&index=4 Part 2] [https://www.youtube.com/watch?v=55w6EXRSR1M&list=PL4if6jkKNTz9RgsB4Gq_g374b4oLYOAeH&index=5 Part 3]
 
|
 
|
 +
* Lab 07: CS Amplifier and Frequency Response
 
|-
 
|-
 
| style="text-align:center;" | 8
 
| style="text-align:center;" | 8
Line 130: Line 133:
 
* Slides: High-Swing Current Sources [https://drive.google.com/file/d/15dsEE2jcVoUNasZmvCOlewN77UxfOieB/view?usp=sharing PDF]
 
* Slides: High-Swing Current Sources [https://drive.google.com/file/d/15dsEE2jcVoUNasZmvCOlewN77UxfOieB/view?usp=sharing PDF]
 
|
 
|
 +
* Lab 08: Current Mirrors and CS Amplifiers with Active Loads
 
|-
 
|-
 
| style="text-align:center;" | 9
 
| style="text-align:center;" | 9
Line 144: Line 148:
 
* Slides: Miller Op-Amp [https://drive.google.com/file/d/1ARDhJZ5SXZ9aMOgDCBVHqwkQAiG0FLsn/view?usp=sharing PDF]
 
* Slides: Miller Op-Amp [https://drive.google.com/file/d/1ARDhJZ5SXZ9aMOgDCBVHqwkQAiG0FLsn/view?usp=sharing PDF]
 
|
 
|
 +
* Lab 09: Differential Pairs and Two-Stage MOS OTA
 
|-
 
|-
 
| style="text-align:center;" | 10
 
| style="text-align:center;" | 10
Line 155: Line 160:
 
* Slides: Folded Cascode [https://drive.google.com/file/d/1Tg0ZyYzh-rQPGdOqmonEXNXNYPkhJ-aW/view?usp=sharing PDF]
 
* Slides: Folded Cascode [https://drive.google.com/file/d/1Tg0ZyYzh-rQPGdOqmonEXNXNYPkhJ-aW/view?usp=sharing PDF]
 
|
 
|
 +
* Lab 10: (Project) Design of a Folded Cascode OTA
 
|-
 
|-
 
|}
 
|}

Latest revision as of 08:13, 27 June 2022

  • Introduction to Analog and Digital Integrated Circuit Design
  • Semester Offered: 2nd semester
  • Course Credit: Lecture: 3 units (2 units lecture, 1 unit lab)

Catalog Description

IC Fabrication. CMOS gates. Logical Effort. Interconnect. Memory Elements. MOS Amplifiers. Current Sources. Differential Amplifiers. Operational Transconductance Amplifiers. Pre-req: EEE 41 or EEE 131. 5h (2 lec, 3 lab) 3 u.

Syllabus

Module Topics Outcomes Resources Activities
Part I: Digital Integrated Circuits
1
  • Identify the key characteristics and non-idealities of a CMOS fabrication process.
  • Analyze how these key characteristics and non-idealities change the characteristics of the devices that will be built on it.
2
  • Simplify the analysis of a CMOS inverter using switch-level transistor models.
  • Determine key CMOS inverter metrics and understand their significance in the analysis and design process.
  • Slides: MOS PDF
  • Slides: CMOS Inverter PDF
  • Lab 02: The MOSFET Switch and The Inverter
3
  • Design CMOS static gates
  • Estimate delays of cascaded logic gates
  • Design multistage networks for optimal speed
  • Slides: CMOS Gates PDF
  • Slides: Logical Effort PDF
  • CoE197U-A3.1: Logical Effort
  • Lab 03: Inverter Characteristics, Ring Oscillator, and Buffers
4
  • Identify sources of power and energy consumption in digital circuits
  • Evaluate energy efficient techniques for digital logic using defined metrics
  • Model interconnects as parasitic resistances and capacitances and estimate corresponding delay
  • Slides: Power and Energy PDF
  • Slides: Interconnects PDF
  • Lab 04 : Static Logic Gates and Logical Effort
5
  • Enumerate and distinguish different memory element classifications
  • Identify timing parameters relevant to memory elements and their effects on sequential circuit timing
  • Design and characterize basic memory elements
  • Slides: Memory PDF
  • Slides: Timing PDF
Part II: Analog Integrated Circuits
6
  • MOS Amplifiers: DC and AC Analysis
  • Determine the DC operating point of MOS amplifiers.
  • Extract the MOS small-signal parameters depending on the DC operating point.
  • Analyze MOS amplifiers in the AC and DC domain.
  • Derive the two-port network representation of MOS amplifiers.
  • Identify the appropriate application of a MOS amplifier topology based on its two-port parameters.
  • Lab 06: Introduction to Analog Design
7
  • MOS Amplifiers: Frequency Response
  • Analyze MOS amplifiers in the frequency domain.
  • Sketch the Bode plots of the transfer function.
  • Estimate the dominant pole using ZVTCA.
  • Lab 07: CS Amplifier and Frequency Response
8
  • Current Sources
  • High-Swing Current Sources
  • Understand ideal and real sources
  • Analyze MOS simple current mirror
  • Analyze High-swing current sources
  • Slides: Current Sources PDF
  • Slides: High-Swing Current Sources PDF
  • Lab 08: Current Mirrors and CS Amplifiers with Active Loads
9
  • Understand differential circuits
  • Analyze MOS differential pairs
  • Understand operational amplifier operation
  • Analyze Miller Operational Amplifiers
  • Slides: MOS Differential Pairs PDF
  • Slides: Miller Op-Amp PDF
  • Lab 09: Differential Pairs and Two-Stage MOS OTA
10
  • Folded Cascode Operational Transconductance Amplifiers
  • Identify the different stages in a folded cascode OTA.
  • Determine the components and/or parameters that affect the DC operating point of a folded cascode OTA.
  • Explain how to design a folded cascode OTA.
  • Slides: Folded Cascode PDF
  • Lab 10: (Project) Design of a Folded Cascode OTA

References

  • Rabaey, Chandrakasan, Nikolic, Digital Integrated Circuits, 2ed., Pearson 2002.
  • Gray, Hurst, Lewis, Meyer, Analysis & Design of Analog Integrated Circuits, Wiley 2001.
  • Johns, Martin, Analog Integrated Circuit Design, Wiley 1997.
  • Design of Analog CMOS Integrated Circuits, Behzad Razavi, McGraw-Hill, 2000.
  • R. Jacob Baker, Circuit Design, Layout,and Simulation, 4ed., IEEE Press 2019.
Retrieved from "https://classes.up-microlab.org/index.php?title=CoE_197U_S2_AY_2021-2022&oldid=3906"