Difference between revisions of "CoE 197U S2 AY 2021-2022"
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* Design multistage networks for optimal speed | * Design multistage networks for optimal speed | ||
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− | * Slides: CMOS Gates [https://drive.google.com/file/d/ | + | * Slides: CMOS Gates [https://drive.google.com/file/d/10McCC1megDnllbIMj7rdtBlyZB84QVBh/view?usp=sharing PDF] |
− | * Slides: Logical Effort [https://drive.google.com/file/d/ | + | * Slides: Logical Effort [https://drive.google.com/file/d/10dGqE_NolixkYaL7aUWMlwPaIILprEFg/view?usp=sharing PDF] |
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* [[CoE197U-A3.1]]: Logical Effort | * [[CoE197U-A3.1]]: Logical Effort | ||
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* Model interconnects as parasitic resistances and capacitances and estimate corresponding delay | * Model interconnects as parasitic resistances and capacitances and estimate corresponding delay | ||
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− | * Slides: Power and Energy [https://drive.google.com/file/d/ | + | * Slides: Power and Energy [https://drive.google.com/file/d/1gbC7LNLFHcncVy0QKoAVykm5zr6tY8D5/view?usp=sharing PDF] |
* Slides: Interconnects [https://drive.google.com/file/d/1Or0KnHb3v0awBcXZHd8CfN2oEP5l3cRj/view?usp=sharing PDF] | * Slides: Interconnects [https://drive.google.com/file/d/1Or0KnHb3v0awBcXZHd8CfN2oEP5l3cRj/view?usp=sharing PDF] | ||
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− | * Lab 04 : Static Logic Gates and Logical Effort | + | * [https://uvle.upd.edu.ph/mod/resource/view.php?id=199635 Lab 04] : Static Logic Gates and Logical Effort |
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| style="text-align:center;" | 5 | | style="text-align:center;" | 5 | ||
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* Design and characterize basic memory elements | * Design and characterize basic memory elements | ||
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− | * Slides: Memory [https://drive.google.com/file/d/ | + | * Slides: Memory [https://drive.google.com/file/d/1h4k-rx-d1iNcbZrvv6cD3GcNqs5GzNIj/view?usp=sharing PDF] |
− | * Slides: Timing [https://drive.google.com/file/d/ | + | * Slides: Timing [https://drive.google.com/file/d/1hA5C63P1zuBascs2_n4ZI_m2XzpEhAQ-/view?usp=sharing PDF] |
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* [[CoE197U-A5.1]]: Timing | * [[CoE197U-A5.1]]: Timing | ||
− | * Lab 05 : Power Delay Product and Memory Elements | + | * [https://uvle.upd.edu.ph/mod/resource/view.php?id=199751 Lab 05] : Power Delay Product and Memory Elements |
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| style="text-align:center;" colspan="5" | ''Part II: Analog Integrated Circuits'' | | style="text-align:center;" colspan="5" | ''Part II: Analog Integrated Circuits'' |
Latest revision as of 08:13, 27 June 2022
- Introduction to Analog and Digital Integrated Circuit Design
- Semester Offered: 2nd semester
- Course Credit: Lecture: 3 units (2 units lecture, 1 unit lab)
Catalog Description
IC Fabrication. CMOS gates. Logical Effort. Interconnect. Memory Elements. MOS Amplifiers. Current Sources. Differential Amplifiers. Operational Transconductance Amplifiers. Pre-req: EEE 41 or EEE 131. 5h (2 lec, 3 lab) 3 u.
Syllabus
Module | Topics | Outcomes | Resources | Activities |
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Part I: Digital Integrated Circuits | ||||
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Part II: Analog Integrated Circuits | ||||
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References
- Rabaey, Chandrakasan, Nikolic, Digital Integrated Circuits, 2ed., Pearson 2002.
- Gray, Hurst, Lewis, Meyer, Analysis & Design of Analog Integrated Circuits, Wiley 2001.
- Johns, Martin, Analog Integrated Circuit Design, Wiley 1997.
- Design of Analog CMOS Integrated Circuits, Behzad Razavi, McGraw-Hill, 2000.
- R. Jacob Baker, Circuit Design, Layout,and Simulation, 4ed., IEEE Press 2019.