Difference between revisions of "CoE 197U"

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== Catalog Description ==
 
== Catalog Description ==
−
IC Fabrication. CMOS gates. Logical Effort. Interconnect. Memory Elements. MOS Amplifiers. Current Sources. Differential Amplifiers. Operational Transconductance Amplifiers. Pre-req: EEE 41 or EEE 131. 5h (2 lec, 3 lab) 4 u.
+
IC Fabrication. CMOS gates. Logical Effort. Interconnect. Memory Elements. MOS Amplifiers. Current Sources. Differential Amplifiers. Operational Transconductance Amplifiers. Pre-req: EEE 41 or EEE 131. 5h (2 lec, 3 lab) 3 u.
  
 
== Syllabus ==
 
== Syllabus ==
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| style="text-align:center;" | 1
 
| style="text-align:center;" | 1
 
|  
 
|  
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* Introduction
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* [[CoE 197U Introduction | Introduction]]
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* [[CoE 197U IC Fabrication | IC Fabrication ]]
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* [[CoE 197U IC Fabrication | IC Fabrication]]
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* Scaling
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* [[CoE 197U Scaling | Scaling]]
 
|  
 
|  
 
* Identify the key characteristics and non-idealities of a CMOS fabrication process.
 
* Identify the key characteristics and non-idealities of a CMOS fabrication process.
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|  
 
|  
 
* Video: Silicon Run I (1996) [https://www.youtube.com/watch?v=3XTWXRj24GM Youtube link]
 
* Video: Silicon Run I (1996) [https://www.youtube.com/watch?v=3XTWXRj24GM Youtube link]
−
* [[ngspice Tutorial]]
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* Paolo Gargini's [https://www.dropbox.com/s/6eskh6bwdcuzpsa/1507_11_Paolo%20Overview_Out.pdf presentation] from the 2015 [http://www.itrs2.net/ International Technology Roadmap for Semiconductors] (ITRS) Summer Meeting.
 
|
 
|
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* [[CoE197U-A1.1]]: IC fabrication
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* [[CoE197U-A1.1]]: IC Fabrication and Scaling
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* [[CoE197U-A1.2]]: MOSFET Characteristics
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* [https://drive.google.com/drive/folders/1PFmtjlx1usOf73PzcLBfkcS8VhDb2Pz8?usp=sharing Lab 00]: Introduction to LTspice
 
|-
 
|-
 
| style="text-align:center;" | 2
 
| style="text-align:center;" | 2
 
|  
 
|  
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* The MOS Switch
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* [[CoE 197U The MOS Transistor | The MOS Transistor]]
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* The CMOS Inverter
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* [[CoE 197U The MOS Switch | The MOS Switch]]
 +
* [[CoE 197U The CMOS Inverter | The CMOS Inverter]]
 
|  
 
|  
 +
* Simplify the analysis of a CMOS inverter using switch-level transistor models.
 +
* Determine key CMOS inverter metrics and understand their significance in the analysis and design process.
 
|  
 
|  
 
|
 
|
 +
* [https://drive.google.com/drive/folders/1lW3RflMSI0DUz3Rb2CCvzhABtaKJXQRt?usp=sharing Lab 01]: The MOSFET Switch and The Inverter
 
|-
 
|-
 
| style="text-align:center;" | 3
 
| style="text-align:center;" | 3
 
|  
 
|  
−
* Static CMOS Gates
+
* [[ CoE 197U CMOS Gates | Static CMOS Gates ]]
−
* Logical Effort
+
* [[ CoE 197U Logical Effort | Logical Effort and Delay ]]
 
|  
 
|  
 +
* Design CMOS static gates
 +
* Estimate delays of cascaded logic gates
 +
* Design multistage networks for optimal speed
 
|  
 
|  
 +
* Slides: CMOS Gates [https://drive.google.com/file/d/1Ohu6h00q8o3mN6PfKG0_ArZ7F97qvOji/view?usp=sharing PDF]
 +
* Slides: Logical Effort [https://drive.google.com/file/d/1OmX857DUfy0X_asE1DKYCIrr9TwwMMvX/view?usp=sharing PDF]
 
|
 
|
 +
* [[CoE197U-A3.1]]: Logical Effort
 +
* [https://drive.google.com/drive/folders/1IaQsQZEfm57A4HbENHF_BZrPzi_iwLzQ?usp=sharing Lab 02]: Inverter Characteristics, Ring Oscillator, and Buffers
 
|-
 
|-
 
| style="text-align:center;" | 4
 
| style="text-align:center;" | 4
 
|  
 
|  
−
* Power, Energy and Delay
+
* [[ CoE 197U Power and Energy | Power and Energy ]]
−
* Interconnect
+
* [[ CoE 197U Interconnects | Interconnects ]]
 
|  
 
|  
 +
* Identify sources of power and energy consumption in digital circuits
 +
* Evaluate energy efficient techniques for digital logic using defined metrics
 +
* Model interconnects as parasitic resistances and capacitances and estimate corresponding delay
 
|  
 
|  
 +
* Slides: Power and Energy [https://drive.google.com/file/d/1OpKOIEaYL6B4tIJ4WBeFDanvIL5H-3RE/view?usp=sharing PDF]
 +
* Slides: Interconnects [https://drive.google.com/file/d/1Or0KnHb3v0awBcXZHd8CfN2oEP5l3cRj/view?usp=sharing PDF]
 
|
 
|
 +
* [https://drive.google.com/drive/folders/1HtOJQGC0XJqgDrctXn14LnqV1bDGPJv4?usp=sharing Lab 03] : Static Logic Gates and Power-Delay Product
 
|-
 
|-
 
| style="text-align:center;" | 5
 
| style="text-align:center;" | 5
 
|
 
|
−
* Memory Elements
+
* [[ CoE 197U Memory | Memory Elements ]]
−
* Timing
+
* [[ CoE 197U Timing | Timing ]]
 
|  
 
|  
 +
* Enumerate and distinguish different memory element classifications
 +
* Identify timing parameters relevant to memory elements and their effects on sequential circuit timing
 +
* Design and characterize basic memory elements
 
|  
 
|  
 +
* Slides: Memory [https://drive.google.com/file/d/1PEUGraNKqPlbqWAljKm1onDU_kUUpk2S/view?usp=sharing PDF]
 +
* Slides: Timing [https://drive.google.com/file/d/1PEg80QK6j8bnSphWYS9hCrJ-gEOLGuyz/view?usp=sharing PDF]
 +
* Slides: Timing Discussion [https://drive.google.com/file/d/1TvtFsCeWpNUtuFKQrUlx80oc0gTxrYhF/view?usp=sharing PDF]
 
|
 
|
 +
* [[CoE197U-A5.1]]: Timing
 +
* [https://drive.google.com/drive/folders/1blJPdFy2G7IbzKCFb-2kXf1_vAcJGQ9O?usp=sharing Lab 04] : Basic Memory Devices
 
|-
 
|-
 
| style="text-align:center;" colspan="5" | ''Part II: Analog Integrated Circuits''
 
| style="text-align:center;" colspan="5" | ''Part II: Analog Integrated Circuits''
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| style="text-align:center;" | 6
 
| style="text-align:center;" | 6
 
|
 
|
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* MOS Amplifiers: DC Analysis
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* MOS Amplifiers: DC and AC Analysis
−
* MOS Amplifiers: Frequency Response
+
|
 +
* Determine the DC operating point of MOS amplifiers.
 +
* Extract the MOS small-signal parameters depending on the DC operating point.
 +
* Analyze MOS amplifiers in the AC and DC domain.
 +
* Derive the two-port network representation of MOS amplifiers.
 +
* Identify the appropriate application of a MOS amplifier topology based on its two-port parameters.
 
|
 
|
−
|
+
* Slides: DC and AC Analysis [https://drive.google.com/file/d/1J5bNkvjyJ5dF0HWpcLABiQq9WOlnyqje/view?usp=sharing PDF]
 +
* Videos: [https://www.youtube.com/watch?v=4tEYeFiYwWI&list=PL4if6jkKNTz9RgsB4Gq_g374b4oLYOAeH&index=1 Part 1] [https://www.youtube.com/watch?v=lD7ejAl4Ue4&list=PL4if6jkKNTz9RgsB4Gq_g374b4oLYOAeH&index=2 Part 2]
 
|
 
|
 
|-
 
|-
 
| style="text-align:center;" | 7
 
| style="text-align:center;" | 7
 
|
 
|
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* Current Sources
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* MOS Amplifiers: Frequency Response
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* High-Swing Current Sources
+
|
−
|  
+
* Analyze MOS amplifiers in the frequency domain.
−
|
+
* Sketch the Bode plots of the transfer function.
 +
* Estimate the dominant pole using ZVTCA.
 +
|
 +
* Slides: Frequency Response [https://drive.google.com/file/d/1IA9OF95XS4FV852IuIpbY5iy1KquA4VI/view?usp=sharing PDF]
 +
* Videos: [https://www.youtube.com/watch?v=1AzlCV_AXgg&list=PL4if6jkKNTz9RgsB4Gq_g374b4oLYOAeH&index=3 Part 1] [https://www.youtube.com/watch?v=I3I6CBye0rU&list=PL4if6jkKNTz9RgsB4Gq_g374b4oLYOAeH&index=4 Part 2] [https://www.youtube.com/watch?v=55w6EXRSR1M&list=PL4if6jkKNTz9RgsB4Gq_g374b4oLYOAeH&index=5 Part 3]
 
|
 
|
 
|-
 
|-
 
| style="text-align:center;" | 8
 
| style="text-align:center;" | 8
 +
|
 +
* Current Sources
 +
* High-Swing Current Sources
 
|  
 
|  
−
* MOS Differential Pairs
+
* Understand ideal and real sources
−
|
+
* Analyze MOS simple current mirror
 +
* Analyze High-swing current sources
 
|  
 
|  
 +
* Slides: Current Sources [https://drive.google.com/file/d/19jU1NupCk66ta6Q3tJyWFYDUagqaZCQs/view?usp=sharing PDF]
 +
* Slides: High-Swing Current Sources [https://drive.google.com/file/d/15dsEE2jcVoUNasZmvCOlewN77UxfOieB/view?usp=sharing PDF]
 
|
 
|
 
|-
 
|-
 
| style="text-align:center;" | 9
 
| style="text-align:center;" | 9
−
|
 
−
* Two-Stage MOS Operational Transconductance Amplifiers
 
 
|  
 
|  
 +
* [[ CoE 197U MOS Differential Pairs | MOS Differential Pairs ]]
 +
* [[ CoE 197U Two-Stage MOS Operational Transconductance Amplifiers | Two-Stage MOS OTA ]]
 +
|
 +
* Understand differential circuits
 +
* Analyze MOS differential pairs
 +
* Understand operational amplifier operation
 +
* Analyze Miller Operational Amplifiers
 
|  
 
|  
 +
* Slides: MOS Differential Pairs [https://drive.google.com/file/d/10p4T9_5qMXiXPeVU0B0yHmzmtTabiQ43/view?usp=sharing PDF]
 +
* Slides: Miller Op-Amp [https://drive.google.com/file/d/1ARDhJZ5SXZ9aMOgDCBVHqwkQAiG0FLsn/view?usp=sharing PDF]
 
|
 
|
 
|-
 
|-
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* Folded Cascode Operational Transconductance Amplifiers
 
* Folded Cascode Operational Transconductance Amplifiers
 
|  
 
|  
 +
* Identify the different stages in a folded cascode OTA.
 +
* Determine the components and/or parameters that affect the DC operating point of a folded cascode OTA.
 +
* Explain how to design a folded cascode OTA.
 
|  
 
|  
−
|
+
* Slides: Folded Cascode [https://drive.google.com/file/d/1Tg0ZyYzh-rQPGdOqmonEXNXNYPkhJ-aW/view?usp=sharing PDF]
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* Johns, Martin, Analog Integrated Circuit Design, Wiley 1997.
 
* Johns, Martin, Analog Integrated Circuit Design, Wiley 1997.
 
* Design of Analog CMOS Integrated Circuits, Behzad Razavi, McGraw-Hill, 2000.
 
* Design of Analog CMOS Integrated Circuits, Behzad Razavi, McGraw-Hill, 2000.
 +
* R. Jacob Baker, Circuit Design, Layout,and Simulation, 4ed., IEEE Press 2019.

Latest revision as of 18:09, 7 May 2021

  • Introduction to Analog and Digital Integrated Circuit Design
  • Semester Offered: 2nd semester
  • Course Credit: Lecture: 3 units (2 units lecture, 1 unit lab)

Catalog Description

IC Fabrication. CMOS gates. Logical Effort. Interconnect. Memory Elements. MOS Amplifiers. Current Sources. Differential Amplifiers. Operational Transconductance Amplifiers. Pre-req: EEE 41 or EEE 131. 5h (2 lec, 3 lab) 3 u.

Syllabus

Module Topics Outcomes Resources Activities
Part I: Digital Integrated Circuits
1
  • Identify the key characteristics and non-idealities of a CMOS fabrication process.
  • Analyze how these key characteristics and non-idealities change the characteristics of the devices that will be built on it.
2
  • Simplify the analysis of a CMOS inverter using switch-level transistor models.
  • Determine key CMOS inverter metrics and understand their significance in the analysis and design process.
  • Lab 01: The MOSFET Switch and The Inverter
3
  • Design CMOS static gates
  • Estimate delays of cascaded logic gates
  • Design multistage networks for optimal speed
  • Slides: CMOS Gates PDF
  • Slides: Logical Effort PDF
  • CoE197U-A3.1: Logical Effort
  • Lab 02: Inverter Characteristics, Ring Oscillator, and Buffers
4
  • Identify sources of power and energy consumption in digital circuits
  • Evaluate energy efficient techniques for digital logic using defined metrics
  • Model interconnects as parasitic resistances and capacitances and estimate corresponding delay
  • Slides: Power and Energy PDF
  • Slides: Interconnects PDF
  • Lab 03 : Static Logic Gates and Power-Delay Product
5
  • Enumerate and distinguish different memory element classifications
  • Identify timing parameters relevant to memory elements and their effects on sequential circuit timing
  • Design and characterize basic memory elements
  • Slides: Memory PDF
  • Slides: Timing PDF
  • Slides: Timing Discussion PDF
Part II: Analog Integrated Circuits
6
  • MOS Amplifiers: DC and AC Analysis
  • Determine the DC operating point of MOS amplifiers.
  • Extract the MOS small-signal parameters depending on the DC operating point.
  • Analyze MOS amplifiers in the AC and DC domain.
  • Derive the two-port network representation of MOS amplifiers.
  • Identify the appropriate application of a MOS amplifier topology based on its two-port parameters.
7
  • MOS Amplifiers: Frequency Response
  • Analyze MOS amplifiers in the frequency domain.
  • Sketch the Bode plots of the transfer function.
  • Estimate the dominant pole using ZVTCA.
8
  • Current Sources
  • High-Swing Current Sources
  • Understand ideal and real sources
  • Analyze MOS simple current mirror
  • Analyze High-swing current sources
  • Slides: Current Sources PDF
  • Slides: High-Swing Current Sources PDF
9
  • Understand differential circuits
  • Analyze MOS differential pairs
  • Understand operational amplifier operation
  • Analyze Miller Operational Amplifiers
  • Slides: MOS Differential Pairs PDF
  • Slides: Miller Op-Amp PDF
10
  • Folded Cascode Operational Transconductance Amplifiers
  • Identify the different stages in a folded cascode OTA.
  • Determine the components and/or parameters that affect the DC operating point of a folded cascode OTA.
  • Explain how to design a folded cascode OTA.
  • Slides: Folded Cascode PDF

References

  • Rabaey, Chandrakasan, Nikolic, Digital Integrated Circuits, 2ed., Pearson 2002.
  • Gray, Hurst, Lewis, Meyer, Analysis & Design of Analog Integrated Circuits, Wiley 2001.
  • Johns, Martin, Analog Integrated Circuit Design, Wiley 1997.
  • Design of Analog CMOS Integrated Circuits, Behzad Razavi, McGraw-Hill, 2000.
  • R. Jacob Baker, Circuit Design, Layout,and Simulation, 4ed., IEEE Press 2019.
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