Difference between revisions of "CoE 197U S2 AY 2023-2024"

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* [https://drive.google.com/file/d/1IgdNWWsXWqQegJP914KjZ7m4zVZ5LEQo/view?usp=sharing HW] Module 3 HW (final extension May 5)
 
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Revision as of 15:18, 6 February 2024

  • Introduction to Analog and Digital Integrated Circuit Design
  • Semester Offered: 2nd semester
  • Course Credit: Lecture: 3 units (2 units lecture, 1 unit lab)

Catalog Description

IC Fabrication. CMOS gates. Logical Effort. Interconnect. Memory Elements. MOS Amplifiers. Current Sources. Differential Amplifiers. Operational Transconductance Amplifiers.

Pre-req: EEE 41 or EEE 131. 5h (2 lec, 3 lab) 3 u.

Schedule of Classes

Lecture: WF 10-11 am

Laboratory: M 10am-1 pm OR Th 2:30-5:30

Mode of Delivery

For lecture, it will be a mix of face-to-face, and synchronous and asynchronous remote learning.

For laboratory, it will be face-to-face at Rm 403.

Syllabus

Module Topics Outcomes Resources Activities
Part I: Digital Integrated Circuits
0

Feb 12-16

  • CoE 197U Orientation
  • Set class expectations, discuss grading system
  • Introduction to CoE 197U
  • Syllabus [PDF]
  • Lab orientation
1

Feb 19-23

  • Identify the key characteristics and non-idealities of a CMOS fabrication process.
  • Analyze how these key characteristics and non-idealities change the characteristics of the devices that will be built on it.
  • CoE197U-A1.1: IC Fabrication and Scaling
  • Lab 01: Introduction to Digital IC Design (MOS Characterization)
2

Feb 26-Mar 1

  • Simplify the analysis of a CMOS inverter using switch-level transistor models.
  • Determine key CMOS inverter metrics and understand their significance in the analysis and design process.
  • Slides: MOS [PDF]
  • Slides: CMOS Inverter [PDF]
  • Recording: Module Discussion [Video]

Lab 02: CMOS Inverter

3

Mar 4-8

  • Design CMOS static gates
  • Estimate delays of cascaded logic gates
  • Design multistage networks for optimal speed
  • Slides: CMOS Gates [PDF]
  • Slides: Logical Effort [PDF]
  • Additional Slides: LE Example [PDF]
  • HW Module 3 HW (final extension May 5)
  • Lab 03: Static CMOS Gates
4

Mar 11-15

  • Identify sources of power and energy consumption in digital circuits
  • Evaluate energy efficient techniques for digital logic using defined metrics
  • Model interconnects as parasitic resistances and capacitances and estimate corresponding delay
  • Slides: Power and Energy [PDF]
  • Slides: Interconnects [PDF]
  • Lab 04: Delay Optimization and Considerations in Digital Design
5

Mar 18-22

  • Enumerate and distinguish different memory element classifications
  • Identify timing parameters relevant to memory elements and their effects on sequential circuit timing
  • Design and characterize basic memory elements
  • Slides: Memory [PDF]
  • Slides: Timing [PDF]
  • Slides: Optional materials [PDF]
  • Video: Module discussion [Link]
  • 2019 Exam: [PDF]
  • Lab 05: Timing and Memory
March 23: Long Exam 1
Part II: Analog Integrated Circuits
6

Apr 8-12

  • MOS Amplifiers: DC and AC Analysis
  • Determine the DC operating point of MOS amplifiers.
  • Extract the MOS small-signal parameters depending on the DC operating point.
  • Analyze MOS amplifiers in the AC and DC domain.
  • Derive the two-port network representation of MOS amplifiers.
  • Identify the appropriate application of a MOS amplifier topology based on its two-port parameters.
7

Apr 15-19

  • MOS Amplifiers: Frequency Response
  • Analyze MOS amplifiers in the frequency domain.
  • Sketch the Bode plots of the transfer function.
  • Estimate the dominant pole using ZVTCA.
8

Apr 22-26

  • Current Sources
  • High-Swing Current Sources
  • Understand ideal and real sources
  • Analyze MOS simple current mirror
  • Analyze High-swing current sources
9

Apr 29-May 3

  • Understand differential circuits
  • Analyze MOS differential pairs
  • Understand operational amplifier operation
  • Analyze Miller Operational Amplifiers
10

May 6-10

  • Folded Cascode Operational Transconductance Amplifiers
  • Identify the different stages in a folded cascode OTA.
  • Determine the components and/or parameters that affect the DC operating point of a folded cascode OTA.
  • Explain how to design a folded cascode OTA.
  • Slides: Folded Cascode [PDF]
May 18: Long Exam 2

Grade distribution

60% Laboratory 30% Long Exams 10% Lecture Class Participation

References

  • Rabaey, Chandrakasan, Nikolic, Digital Integrated Circuits, 2ed., Pearson 2002.
  • Gray, Hurst, Lewis, Meyer, Analysis & Design of Analog Integrated Circuits, Wiley 2001.
  • Johns, Martin, Analog Integrated Circuit Design, Wiley 1997.
  • Design of Analog CMOS Integrated Circuits, Behzad Razavi, McGraw-Hill, 2000.
  • R. Jacob Baker, Circuit Design, Layout,and Simulation, 4ed., IEEE Press 2019.
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