CoE 197U Timing

In this lecture, we will cover the following topics:

• Register timing basics
• Timing Uncertainty
• Clock distribution

Use the provided slide deck to guide you through this discussion. The main reference for this lecture is the Digital IC book

Note that the slide deck contains information for both latch and register. In this discussion, we focus only on register timing.

Timing Basics

Shown in Fig. 1 is an illustration of the timing parameters of a register. Important parameters here are setup time (t_su), hold time (t_H), clock-to-Q delay (t_clk-q) and clock period (T_clk). Setup time is the minimum time required that the input data, D, has to be stable before the edge of the CLK. Hold time, on the other hand, is the minimum time required for data, D, to remain stable after the edge of the clock. The clk-to-q delay, as the name implies, is the time after the edge of the clock when the output, Q, is considered valid.

Given the register timing parameters, we can compute for the clock period and hold time constraints of a sequential circuit. This is illustrated in Fig. 2. Corresponding equations are also shown in the figure.