CoE 197U Two-Stage MOS Operational Transconductance Amplifiers

If a larger gain than that of a differential amplifier is needed, the next step is to use cascade amplifier stage/s or cascode the differential pair. Cascoding uses common-gate amplifiers/buffers to increase gain at the cost of reduced voltage swing. Meanwhile, cascading can achieve larger voltage swings but need separate current paths and therefore, consume more power. With nominal supply voltages decreasing with technology, cascoding becomes less viable. In this lecture, we will look at a typical 2-stage MOS amplifier.

The main reference for this topic is chapter 6.3 of the Analysis and Design of Analog Integrated Circuits book.

Op-amps and OTA

An operational amplifier or op-amp can be roughly divided into three stages (Fig. 1): the differential pair, the gain stage/s, and the output stage. The differential pair enables the op-amp to have a differential input, have a large input resistance, and provide some gain. The gain stage/s provide the additional gain needed, but in doing so, end up with a large output resistance that cannot drive heavy (low resistance) resistive loads. The output stage provides a gain of 1 or less. It is added to give the op-amp low output resistance, large output swing, and the ability to provide large output currents.

Figure 1: Generalized op-amp blocks

Figure 2: Op-amp symbol visualized as a combination of an OTA symbol and a buffer

The differential and gain stages combined can be viewed as an OTA or operational transconductance amplifier. Thus, the op-amp can be viewed as an OTA with an output buffer (Fig. 2). OTAs have large gain and large output resistance. An OTA produces an output current from an input voltage and can drive capacitive loads (provide charging current) which are common in on-chip loads (e.g. gate of another MOSFET). A low output resistance is not necessarily required in driving capacitive loads.

Miller OTA

The Miller OTA is a simple 2-stage OTA composed of a current mirror-loaded differential pair stage and a common source stage (Fig. 3). It is one of the go-to amplifiers in IC design because of its simplicity. The topology contains only a few transistors, making it relatively easy to design. The circuit also has a simple biasing scheme. The design of the current source itself is a different story! However, in less critical applications, a resistor can be used in place of the current source. There are many problems associated with the latter scheme. On-chip resistors are not accurate, may occupy large chip area, can change resistance with temperature, and provides current that is sensitive to temperature and supply voltage changes.

This two-stage OTA can be compensated by using a compensating capacitor, $C_{C}$. Compensation is needed to ensure that the amplifier is stable when used in feedback. You may refer to these materials (please wait for the link to be updated) to review the fundamental concepts of feedback and compensation. If the load capacitance is not large enough to create a dominant pole, then the capacitor $C_{C}$ can be added. Placing a very large capacitor to produce a dominant pole is expensive in terms of chip area. By placing the capacitor $C_{C}$ as shown, a smaller capacitance value (and thus area) is needed since the Miller effect amplifies the capacitance by a factor $g_{m6}\left(r_{o6}\parallel r_{o7}\right)$. This amplified capacitance effectively appears at the input of the common source stage (or output of the differential pair) to ground. With a large enough $C_{C}$, the pole associated with the output of the differential pair can be made dominant to ensure stability.

Before proceeding, note that the analysis to be presented assumes that all transistors are saturated square law devices described by the equations below (for NMOS). The term overdrive voltage or $V_{OV}$ is used to refer to $V_{GS}-V_{TH}$ or $V_{DSAT}$. For PMOS devices, $V_{OV}$ refers to $\left|V_{GS}\right|-\left|V_{TH}\right|$. The paired devices (M1 and M2, and M3 and M4) have the same dimensions. All NMOS transistors are also assumed to have the same threshold voltage $V_{THn}$ while all PMOS transistors are assumed to have the same threshold voltage $V_{THp}$.

$I_{D}={\frac {k'}{2}}{\frac {W}{L}}\left(V_{GS}-V_{TH}\right)^{2}\left(1+\lambda V_{DS}\right)={\frac {k'}{2}}{\frac {W}{L}}\left(V_{OV}\right)^{2}\left(1+\lambda V_{DS}\right)$

$g_{m}={\frac {2I_{D}}{V_{OV}}}={\sqrt {2k'{\frac {W}{L}}I_{D}}}$

$r_{o}={\frac {1}{\lambda I_{D}}}$

AC Analysis (Low Frequency)

The AC characteristics will be discussed first to evaluate the impact of design decisions done when sizing and biasing the transistors at DC. Only very low frequencies are considered such that the capacitor $C_{C}$ is still open and can be disregarded.

Gain

The input resistance of the 2nd stage, the common source stage, is infinite. Thus, there will be no loading between the two stages. The overall low-frequency small-signal gain of the Miller OTA is simply $A_{v}=A_{v,dp}\cdot A_{v,cs}$. From the differential pair discussion , it was shown that the gain of an NMOS-input differential pair is some $g_{mn}\left(r_{on}\parallel r_{op}\right)$. Meanwhile, the gain of a PMOS common source amplifier with an NMOS active load is some $g_{mp}\left(r_{op}\parallel r_{on}\right)$.

$A_{v,dp}=g_{m1}\left(r_{o2}\parallel r_{o4}\right)$

$A_{v,cs}=-g_{m6}\left(r_{o6}\parallel r_{o7}\right)$

$A_{v}=-g_{m1}\left(r_{o2}\parallel r_{o4}\right)\cdot g_{m6}\left(r_{o6}\parallel r_{o7}\right)$

(1)

The differential pair stage’s gain is non-inverting since the negative terminal of the input is at the output side. On the other hand, the common source stage is inverting. The overall gain of the two-stage OTA is inverting. If a non-inverting gain is desired, the input connection can just be switched (positive terminal of the input at M2 gate instead). It can also be said that the gain is related to some $\left(g_{m}r_{o}\right)^{2}$ quantity.

Output Resistance

The output resistance can be determined by grounding the input and placing a test source at the output. Since the input to the differential pair is zero, its output must also be zero. Since the source of M6 is also grounded, then $v_{gs6}=0$. At the bottom, the gate of M7 is connected to some DC bias which is an AC ground. Since the source of M7 is also grounded, then $v_{gs7}=0$. With the help of Fig. 4, it is easy to see that the output impedance is just $r_{o6}$ and $r_{o7}$ in parallel.

$R_{o}=r_{o6}\parallel r_{o7}$

(2)