CoE 197U Memory

In this lecture, we will cover the following topics:

• Classification of Memory
• Static and Dynamic Latches and Registers
• Pipelining

Use the provided slide deck to guide you through this discussion. The main reference for this lecture is the Digital IC book

Memory Classification

Memory can be classified according to different categories. Memory can be either foreground (as part of logic, such as in sequential circuits) or background (as a large storage). Memory can also be classified as either static, that is the data is retained as long as power is ON, or dynamic, where constant refreshing of the data is needed. In sequential circuit, we can also classify memory as either a register (or sometimes referred as flip-flops, meaning edge sensitive) or a latch (meaning level sensitive).

Memory Elements

Static memory rely on the principle of positive feedback to achieve two possible states, or what we call a bistable circuit, represented as either a 0 or a 1. Fig. 1 shows the basic idea of positive feedback, illustrated by 2 inverters connected in a ring. Considering the first inverter, the input is V_i1 and output is V_o1, and the corresponding VTC is shown on the left. For the second inverter, the input is V_i2 = V_o1 and the output is V_o2 = V_i1. So we can flip the VTC as shown on the right, so the axes of both plots coincide. As such, we can combine as shown on the figure at the bottom. Here we can see that we have 3 operating points: A (V_i1=0, V_o1 = 1), B (V_i1 = 1, V_o1 = 0) and C. Point C is known as the metastable state. That is, assuming the inverter pair in Fig. 1 happens to be biased at point C, a small deviation or noise can shift to either point A or point B. This is illustrated in Fig. 2. A small deviation d gets amplified through the inverter pair causing the operating point to shift from C to A and stay at A. From either point A or B, however, even a larger deviation will not shift the operating point, making point A and B stable states.

Fig. 1 Positive Feedback

Fig. 2 Metastability

One possible implementation of the latch is the mux-based, as shown in Fig. 3. Here, while CLK = 1, the lower transmission gate is closed, giving a direct path from D to Q. Once the CLK goes low, the lower transmission gate opens while the top transmission gate closes. Thus the path from D is disconnected while the data in Q gets stored through the inverter pair. A more common latch implementation is the cross-coupled NOR SR latch (may also be implemented using cross-coupled NAND) as shown in Fig. 4.

Fig. 3 MUX-based Latch

Fig. 4 SR Latch

Dynamic latches store data through parasitic capacitances as shown in Fig. 5 on the left. However, the charge on the capacitance may be discharged especially of the clock period is long. As such some refreshing mechanism is needed to ensure that the charge in the capacitor is replenished and therefore data will not be lost. A possible solution to this is the peudo-static latch, where a small keeper inverter is added to provide the positive feedback for the data and therefore no refreshing is necessary.

Fig. 5 Pseudo-static Latch

Registers or edge-triggered flip-flops are typically designed using the master-slave latch, composed of 2 opposite latches as shown in Fig. 6. While CLK=0, the master latch is transparent and therefore Q_M takes the value of D. As CLK switches from 0 to 1, the master latch latches the data from D to Q_M while the slave latch becomes transparent and copies QM to Q. Since the master is now latched, Q_M does not change and therefore, Q also does not change. As such, it would seem that the last data from D that was sampled while CLK goes from 0 to 1 is the one that is kept at Q.

Fig. 6 Master-Slave Latches

Read through the rest of the slides for the related timing parameters of latches and registers.

Pipelining

Pipelining allows improvement of throughput by diving the whole process into several tasks, with each task expected to complete within a single clock cycle. This is illustrated in Fig. 6 below. The reference design completes all tasks in a single cycle. Of course, the clock period will be limited by how long all these processes will complete. The pipelined version inserts registers in between the different sub-tasks to avoid loosing data. Each sub-task will take one cycle, so the clock period will be limited by the slowest sub-task.An advantage of the pipelined version is that inputs a and b may be fed each clock cycle (which is ~3x faster than the reference) and therefore the effective throughput is faster.

Fig. 7 Pipelining

Next: Timing