CoE 197U Interconnects

In this lecture, we will cover topics on wires and interconnects.

Use the provided slide deck to guide you through this discussion. The main reference for this lecture is Chapter 4 of the Digital IC book

Interconnects

Wires are often neglected during design. They are simply used to connect signals from one point to another and assumed to have negligible effect on the performance of the system. Figure 1 shows the widening gap between wire delays and gate delays. As technology scales, dimensions and delays decrease. However, with the thinner interconnects, the wire resistance per unit length increases. As such, degradation in performance can be expected if they are not dealt with properly.

In terms of models, interconnects are represented as parasitics the degrade performance and reduce reliability of the system. Classes of parasistics are capacitive, resistive and inductive. For this course, we consider mostly capacitive and resistive. Any two parallel conductors with a dielectric in between can be treated as a capacitor. This is illustrated in Figure 2 and the corresponding equation shown. Typical CMOS IC uses silicon dioxide as dielectric. The table here shows dielectric constants of other materials.

Any material will have some resistance. The equation is given in the figure, with the corresponding dimensions illustrated. Since the height (H) of the material is dictated by the manufacturing process, and the conductivity (rho) is determined by the material, then we can separate the length and width from the other parameters. The simplest model for interconnects is the lumped model, where total capacitance and total resistance of the conductor is computed and treated as a single RC network.

For long wires, the interconnect can be viewed as cascaded shorter wires, each having its R and C., as shown in the figure. The path delay is computed using the given equation. For a sample problem and solution, you may watch the video: https://www.youtube.com/watch?v=1c_AgRmXQBw.