CoE 197U Logical Effort

In this lecture, we will cover the following:

• Delay Parameters
• Logical Effort of Simple Gates
• Multistage Networks

Use the provided slide deck to guide you through this discussion. The main reference for this lecture is Sutherland's book and paper.

Delay

The delay of a path is equal to the sum of individual gate delays and the delay through the interconnect lines. Each gate delay can be decomposed into its intrinsic delay, p, and the effort delay, f. The effort delay is given by f = gh, where g is the logical effort and h is the effective fanout = C_out / C_in.

Logical Effort

Logical effort is a function of the gate topology and is independent of sizing. It represents the ratio of its input capacitance to the inverter capacitance when size to deliver the same current. The logical effort of the INV, NAND2 and NOR2 are shown in Fig. 1. The simplest gate is the inverter, with an input capacitance of 3C_min (2C_min from pmos and C_min from nmos). For the NAND2, each input sees 2C_min from pmos and 2C_min from nmos, giving a logical effort g = 4/3. The logical effort of other static CMOS gates is shown in Table 1. The parasitic delays of static CMOS gates are shown in Table 2.

Fig. 1. Logical Effort of Static CMOS Gates

Table 1. Logical Effort of Static CMOS Gates

Table 2. Parasitic Delay of Static CMOS Gates

Multistage Networks

The delay