Difference between revisions of "CoE 197U"

From Microlab Classes
Jump to navigation Jump to search
m
Line 123: Line 123:
 
* 3
 
* 3
 
|  
 
|  
 +
* Slides: Frequency Response [https://drive.google.com/file/d/1IA9OF95XS4FV852IuIpbY5iy1KquA4VI/view?usp=sharing PDF]
 +
* Slides: Frequency Response [https://drive.google.com/file/d/1IA9OF95XS4FV852IuIpbY5iy1KquA4VI/view?usp=sharing PDF]
 
|
 
|
 
|-
 
|-

Revision as of 01:31, 13 March 2021

  • Introduction to Analog and Digital Integrated Circuit Design
  • Semester Offered: 2nd semester
  • Course Credit: Lecture: 3 units (2 units lecture, 1 unit lab)

Catalog Description

IC Fabrication. CMOS gates. Logical Effort. Interconnect. Memory Elements. MOS Amplifiers. Current Sources. Differential Amplifiers. Operational Transconductance Amplifiers. Pre-req: EEE 41 or EEE 131. 5h (2 lec, 3 lab) 3 u.

Syllabus

Module Topics Outcomes Resources Activities
Part I: Digital Integrated Circuits
1
  • Identify the key characteristics and non-idealities of a CMOS fabrication process.
  • Analyze how these key characteristics and non-idealities change the characteristics of the devices that will be built on it.
2
  • Simplify the analysis of a CMOS inverter using switch-level transistor models.
  • Determine key CMOS inverter metrics and understand their significance in the analysis and design process.
  • Lab 01: The MOSFET Switch and The Inverter
3
  • Design CMOS static gates
  • Estimate delays of cascaded logic gates
  • Design multistage networks for optimal speed
  • Slides: CMOS Gates PDF
  • Slides: Logical Effort PDF
  • CoE197U-A3.1: Logical Effort
  • Lab 02: Inverter Characteristics, Ring Oscillator, and Buffers
4
  • Identify sources of power and energy consumption in digital circuits
  • Evaluate energy efficient techniques for digital logic using defined metrics
  • Model interconnects as parasitic resistances and capacitances and estimate corresponding delay
  • Slides: Power and Energy PDF
  • Slides: Interconnects PDF
  • Lab 03 : Static Logic Gates and Power-Delay Product
5
  • Memory Elements
  • Timing
  • Enumerate and distinguish different memory element classifications
  • Identify timing parameters relevant to memory elements and their effects on sequential circuit timing
  • Design and characterize basic memory elements
  • Slides: Memory PDF
  • Slides: Timing PDF
  • Lab 04 : Basic Memory Devices
Part II: Analog Integrated Circuits
6
  • MOS Amplifiers: DC and AC Analysis
  • Determine the DC operating point of MOS amplifiers.
  • Extract the MOS small-signal parameters depending on the DC operating point.
  • Analyze MOS amplifiers in the AC and DC domain.
  • Derive the two-port network representation of MOS amplifiers.
  • Identify the appropriate application of a MOS amplifier topology based on its two-port parameters.
  • Slides: DC and AC Analysis PDF
7
  • MOS Amplifiers: Frequency Response
  • Analyze MOS amplifiers in the frequency domain.
  • Sketch the Bode plots of the transfer function.
  • Estimate the dominant pole using ZVTCA.
  • Slides: Frequency Response PDF
8
  • Current Sources
  • High-Swing Current Sources
  • 1
  • 2
  • 3
  • Slides: Frequency Response PDF
  • Slides: Frequency Response PDF
9
  • MOS Differential Pairs
  • Two-Stage MOS Operational Transconductance Amplifiers
10
  • Folded Cascode Operational Transconductance Amplifiers
  • Identify the different stages in a folded cascode OTA.
  • Determine the components and/or parameters that affect the DC operating point of a folded cascode OTA.
  • Explain how to design a folded cascode OTA.

References

  • Rabaey, Chandrakasan, Nikolic, Digital Integrated Circuits, 2ed., Pearson 2002.
  • Gray, Hurst, Lewis, Meyer, Analysis & Design of Analog Integrated Circuits, Wiley 2001.
  • Johns, Martin, Analog Integrated Circuit Design, Wiley 1997.
  • Design of Analog CMOS Integrated Circuits, Behzad Razavi, McGraw-Hill, 2000.
  • R. Jacob Baker, Circuit Design, Layout,and Simulation, 4ed., IEEE Press 2019.