Difference between revisions of "CoE 197U Logical Effort"
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Use the provided slide deck to guide you through this discussion. | Use the provided slide deck to guide you through this discussion. | ||
| − | The main reference for this lecture is Sutherland | + | The main reference for this lecture is Sutherland's book<ref name="sutherland1999">I Sutherland, B Sproull, D. Harris, '''Logical Effort: Designing Fast CMOS Circuits''', Morgan Kaufman Publishers, 1999</ref> and paper<ref name="sutherland1991">I Sutherland, R.F. Sproull, '''Logical Effort: Designing for speed on the back of an envelope''', pp 1-16, 1991</ref>. |
== Delay == | == Delay == | ||
The delay of a path is equal to the sum of individual delays of the gates, | The delay of a path is equal to the sum of individual delays of the gates, | ||
| + | |||
| + | == References == | ||
Revision as of 19:25, 9 March 2021
In this lecture, we will cover the following:
- Delay Parameters
- Logical Effort of Simple Gates
- Multistage Networks
Use the provided slide deck to guide you through this discussion. The main reference for this lecture is Sutherland's book[1] and paper[2].
Delay
The delay of a path is equal to the sum of individual delays of the gates,
