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| | Passive devices such as resistors, capacitors, and inductors, are commonly used in biasing circuits, feedback networks, and signal or energy storage blocks. However, these passive devices, when built on fabrication processes that are optimized for transistors, may have characteristics different from their ideal or discrete counterparts. In this module, we examine the behavior of passive devices built alongside CMOS transistors. | | Passive devices such as resistors, capacitors, and inductors, are commonly used in biasing circuits, feedback networks, and signal or energy storage blocks. However, these passive devices, when built on fabrication processes that are optimized for transistors, may have characteristics different from their ideal or discrete counterparts. In this module, we examine the behavior of passive devices built alongside CMOS transistors. |
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| − | == Resistors ==
| + | We will divide this module into the following sections: |
| − | In standard digital CMOS processes, there is usually no provision for high resistance layers, since resistances are typically deemed bad for digital circuits. But in analog design, we often need well-controlled resistors, with relatively large resistance values.
| + | * [[Integrated Resistors]] |
| | + | * [[Integrated Capacitors]] |
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| − | === Sheet Resistance ===
| + | Read the two modules above, the do the activity below. |
| − | In order to evaluate if a particular layer could be used as to build a resistor, we look to their sheet resistance. Recall that for a resistor:
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| − | {{NumBlk|::|<math>R = \frac{\rho \cdot \ell}{A} = \frac{\rho}{t}\frac{\ell}{w}= R_\mathrm{sh} \frac{\ell}{w}</math>|{{EquationRef|1}}}} | + | {{Note|[[220-A2.1 | '''Activity A2.1''' Integrated Resistors and Capacitors]] -- This activity walks you through the analysis and simulation of integrated RC circuits.|reminder}} |
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| − | Where <math>R_\mathrm{sh}</math> is the ''sheet resistance'' of the layer, <math>\rho</math> is the resistivity of the material, <math>\ell</math> is the length along the direction of the current, and <math>A = w\cdot t</math>, is the cross sectional area normal to the current flow, which is equal to the product of the layer thickness, <math>t</math> and <math>w</math> is the width of the layer perpendicular to the current flow.
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| − | Note that the units of sheet resistance is <math>\mathrm{\Omega/\square}</math> since <math>R_\mathrm{sh}</math> is the resistance of a square, i.e. when <math>\ell = w</math>. Table 1 shows indicative sheet resistance values of the common conductive layers in a CMOS process: | |
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| − | {| class="wikitable" style="text-align: center;"
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| − | |+ Table 1: Sheet Resistances
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| − | |-
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| − | ! Layer
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| − | ! Sheet Resistance
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| − | |-
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| − | | Metal
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| − | | <math>50-70\,\mathrm{m\Omega/\square} \pm 30\mathrm{%}</math>
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| − | |-
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| − | | Polysilicon
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| − | | <math>5\,\mathrm{m\Omega/\square}</math>
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| − | |-
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| − | | <math>n^+</math> or <math>p^+</math> Diffusion
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| − | | <math>5\,\mathrm{m\Omega/\square}</math>
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| − | |-
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| − | | <math>n</math>-well
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| − | | <math>1-5\,\mathrm{k\Omega/\square} \pm 40\mathrm{%}</math>
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| − | |-
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| − | |}
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| − | An illustrative cross-section of resistors using these layers are shown in Figs. 1 and 2.
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| − | | |
| − | {|
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| − | | [[File:Si resistors.png|thumb|520px|Figure 1: Resistors built using semiconductor layers<ref name="Allen2016">Phillip Allen's [https://aicdesign.org/wp-content/uploads/2018/08/lecture03-151116.pdf slides] on Deep Submicron CMOS Technologies</ref>.]]
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| − | | [[File:Metal resistor.png|thumb|450px|Figure 2: Resistors built using metal layers<ref name="Allen2016"/>.]]
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| − | |-
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| − | |}
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| − | [[File:Silicide cmos.png|thumb|300px|Figure 3: Silicide layers on diffusion and polysilicon layers to reduce the effective sheet resistance<ref>Krishna Saraswat's [https://web.stanford.edu/class/ee311/NOTES/Silicides%20&%20Metal%20gate%20Slides.pdf slides] on Polycides, Salicides and Metals Gates.</ref>.]]
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| − | In a CMOS process optimized for digital circuits, the low sheet resistances of the semiconductor layers are due to a low-resistance silicide layer deposited on top of the semiconductor layer, as shown in Fig. 3. In analog CMOS processes, we are usually given the option to place a silicide block, i.e. to prevent the silicide layer from being deposited on specific locations on the die. Table 2 contains illustrative values of the sheet resistance of the semiconductor layers with the silicide block option.
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| − | {| class="wikitable" style="text-align: center;"
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| − | |+ Table 2: Non-Silicided Layer Properties
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| − | |-
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| − | ! Layer
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| − | ! <math>R_\mathrm{sh}\,\mathrm{[\Omega/\square]}</math>
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| − | ! <math>T_C\,\mathrm{[ppm/^\circ C]} \{@}T_0=25^\circ C</math>
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| − | ! <math>V_C\,\mathrm{[ppm/V]}</math>
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| − | ! <math>B_C\,\mathrm{[ppm/V]}</math>
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| − | |-
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| − | | <math>n^+</math>-polysilicon
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| − | | 100
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| − | | -800
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| − | | 50
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| − | | 50
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| − | |-
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| − | | <math>p^+</math>-polysilicon
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| − | | 180
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| − | | 200
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| − | | 50
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| − | | 50
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| − | |-
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| − | | <math>n^+</math>-diffusion
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| − | | 50
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| − | | 1500
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| − | | 500
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| − | | -500
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| − | |-
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| − | | <math>p^+</math>-diffusion
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| − | | 100
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| − | | 1600
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| − | | -500
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| − | | 500
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| − | |-
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| − | | <math>n</math>-well
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| − | | 1000
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| − | | -1500
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| − | | 20,000
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| − | | 30,000
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| − | |-
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| − | |} | |
| − | | |
| − | === Temperature and Voltage Coefficients ===
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| − | In general, semiconductor resistor values change with temperature and applied voltage, and to describe these changes, we use temperature and voltage coefficients:
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| − | {{NumBlk|::|<math>R = R_0\left[1 + T_C\left(T-T_0\right) + V_C\left(V_1-V_2\right) + B_C\left(\frac{V_1 + V_2}{2}-V_B\right) \right]</math>|{{EquationRef|2}}}}
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| − | | |
| − | Where <math>R_0</math> is the nominal resistance value at some reference temperature <math>T_0</math>, <math>T_C</math> is the temperature coefficient, <math>V_C</math> is the voltage coefficient, <math>B_C</math> is the body voltage coefficient, <math>V_1</math> and <math>V_1</math> are the terminal voltages, and <math>V_B</math> is the bulk or body voltage.
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| − | In semiconductors, we know that the resistivity is a strong function of temperature, roughly due to two mechanisms: (1) increasing the temperature increases the number of free carriers, thus lowering the resistance, resulting in negative temperature coefficients, and (2) this increase in free carriers increases the probability of scattering events or collisions, increasing the effective resistance, resulting in positive temperature coefficients. Thus, depending on which mechanism is dominant, we get positive or negative temperature coefficients.
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| − | === Resistor Matching ===
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| − | | |
| − | == Capacitors ==
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| − | | |
| − | == Inductors ==
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| − | == References ==
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| − | <references />
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