Integrated Resistors

In standard digital CMOS processes, there is usually no provision for high resistance layers, since resistances are typically deemed bad for digital circuits. But in analog design, we often need well-controlled resistors, with relatively large resistance values.

Sheet Resistance

Figure 1: Layer resistance parameters.

In order to evaluate if a particular layer could be used as to build a resistor, we look to their sheet resistance. Recall that for a resistor:

$R={\frac {\rho \cdot \ell }{A}}={\frac {\rho }{t}}{\frac {\ell }{w}}=R_{\mathrm {sh} }{\frac {\ell }{w}}$

(1)

Where $R_{\mathrm {sh} }={\tfrac {\rho }{t}}$ is the sheet resistance of the layer, $\rho$ is the resistivity of the material, $\ell$ is the length along the direction of the current, and $A=w\cdot t$, is the cross sectional area normal to the current flow, which is equal to the product of the layer thickness, $t$ and $w$ is the width of the layer perpendicular to the current flow, as shown in Fig. 1. Note that the resistivity, $\rho$, and layer thickness, $t$ are technology specific parameters, and are determined by the fabrication process. The designer can specify resistance values by controlling the width, $w$, and the length, $\ell$.

Note that the units of sheet resistance is $\mathrm {\Omega /\square }$ since $R_{\mathrm {sh} }$ is the resistance of a square, i.e. when $\ell =w$. Table 1 shows indicative sheet resistance values of the common conductive layers in a CMOS process.

Table 1: Sheet Resistances

Layer	Sheet Resistance
Metal	$50-70\,\mathrm {m\Omega /\square } \pm 30\mathrm {\%}$
Polysilicon	$5\,\mathrm {m\Omega /\square }$
$n^{+}$ or $p^{+}$ Diffusion	$5\,\mathrm {m\Omega /\square }$
$n$-well	$1-5\,\mathrm {k\Omega /\square } \pm 40\mathrm {\%}$

An illustrative cross-section of resistors using these layers are shown in Figs. 2 and 3.

Figure 2: Resistors built using semiconductor layers.

Figure 3: Resistors built using metal layers.

Figure 4: Silicide layers on diffusion and polysilicon layers to reduce the effective sheet resistance.

In a CMOS process optimized for digital circuits, the low sheet resistances of the semiconductor layers are due to a low-resistance silicide layer deposited on top of the semiconductor layer, as shown in Fig. 4. In analog CMOS processes, we are usually given the option to place a silicide block, i.e. to prevent the silicide layer from being deposited on specific locations on the die. Table 2 contains illustrative values of the sheet resistance of the semiconductor layers with the silicide block option.

Table 2: Non-Silicided Layer Properties

Layer	$R_{\mathrm {sh} }\,\mathrm {[\Omega /\square ]}$	$T_{C}\,\mathrm {[ppm/^{\circ }C]}$ @$T_{0}=25^{\circ }C$	$V_{C}\,\mathrm {[ppm/V]}$	$B_{C}\,\mathrm {[ppm/V]}$
$n^{+}$-polysilicon	100	-800	50	50
$p^{+}$-polysilicon	180	200	50	50
$n^{+}$-diffusion	50	1500	500	-500
$p^{+}$-diffusion	100	1600	-500	500
$n$-well	1000	-1500	20,000	30,000

Temperature and Voltage Coefficients

In general, semiconductor resistor values change with temperature and applied voltage, and to describe these changes, we use temperature and voltage coefficients:

$R=R_{0}\left[1+T_{C}\left(T-T_{0}\right)+V_{C}\left(V_{1}-V_{2}\right)+B_{C}\left({\frac {V_{1}+V_{2}}{2}}-V_{B}\right)\right]$

(2)

Where $R_{0}$ is the nominal resistance value at some reference temperature $T_{0}$, $T_{C}$ is the temperature coefficient, $V_{C}$ is the voltage coefficient, $B_{C}$ is the body voltage coefficient, $V_{1}$ and $V_{1}$ are the terminal voltages, and $V_{B}$ is the bulk or body or substrate voltage.

In semiconductors, we know that the resistivity is a strong function of temperature, roughly due to two mechanisms: (1) increasing the temperature increases the number of free carriers, thus lowering the resistance, resulting in negative temperature coefficients, and (2) this increase in free carriers increases the probability of scattering events or collisions, increasing the effective resistance, resulting in positive temperature coefficients. Thus, depending on which mechanism is dominant, we get positive or negative temperature coefficients.

The voltage coefficient models the changes in resistance values due to the varying depletion region widths caused by the terminal voltages. On the other hand, for the body voltage coefficient, we use the average voltage across the resistor relative to the substrate voltage.

Resistor Matching

Due to the nature of the manufacturing process steps such as photolithography, chemical and plasma etching, and ion implantation or diffusion doping, the layer dimensions and resistivity could change across wafers, across dies, or even across devices. Collectively we call these changes process variations, and if we are not careful, these variations could degrade the functionality and performance of our circuits. If we lump process variations with voltage and temperature changes, we refer to these as PVT variations.

We can classify process variations as either systematic or random.

• Systematic variations are deterministic variations, i.e. we can predict the changes. This could be due to the manufacturing process such as the existence doping or thickness gradients that results in one side of the wafer having thicker layers which gradually thin out as we get to the other side.
• Random variations are due to random processes such as electron diffusion, or photon scattering that creates random mismatch between devices. Though we cannot predict the actual values that arise from random processes, we can still describe, analyze, and design circuits based on the statistics, such as the mean and variance, of these random variables.

As we see in Table 1, the process variations in resistor values can be as large as $\pm 30\%$. However, if we use ratios of resistors instead of their absolute values, together with good design and layout, we can reduce the mismatch, and in some cases to as low as $0.1\%$.