CoE 197U The MOS Switch

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Levels of Abstraction

As integrated circuits continue to increase in complexity and sophistication, the amount of information and information processing needed to design, fabricate, and test these ICs also increase. Without a way to organize this information, engineers can be easily overwhelmed. One strategy is to define levels of abstraction, where we partition the information, and use only the components needed for a particular task. This strategy can then be used to create models appropriate for a certain objective.

We create models to allow us to predict the behavior of a circuit or system. One approach we can take is to model a whole system using transistor models, e.g. BSIM[1] models, with hundreds of parameters per transistor. The amount of computing resources needed for systems with millions of transistors could render this approach impractical.

In most cases, the overall functionality of a digital system is determined by the system architecture and organization, e.g. is it an adder, or a multiplier, or a microprocessor? At this level, we do not really need to know transistor-level details such as the threshold voltage or the thickness of the gate oxide. Thus, we can abstract away the unneeded information, and retain only the information needed to accomplish the task. By reducing the complexity of the transistor model, we can significantly reduces the amount of computation needed to verify the functionality of the digital system. However, if we want to predict or determine the leakage power consumption of the system, then we need to take into account the transistor threshold voltages, leading to a different simulation strategy and transistor model abstraction.

Fig. 1 shows an example of how a system can be seen from different levels of abstractions or viewpoints, from the system-level, to the architectural-level, the gate-level, the transistor-level, and the physical-level.

Figure 1: Levels of abstraction[2].

What is a Transistor?

Figure 2: The 45nm NMOS PTM[3] output characteristics.

The Ideal Switch

Figure 4: The ideal switch V-I characteristics.

The Switch Model of a Transistor

NMOS vs. PMOS Transistors

References

  1. https://bsim.berkeley.edu/
  2. A. Ghosh, Fault Modeling in Chip Design - VLSI DFT, 2020 (link)
  3. Arizona State University Predictive Technology Models (PTM) website