Integrated Capacitors

Similar to resistors, in a CMOS process optimized for digital circuits, capacitances are treated as parasitic devices that degrade the performance of digital circuits, except in specialized cases such as memory circuits. However, in analog design, we often need capacitors with very well-controlled capacitance values.

Capacitance Geometries

The parallel-plate capacitance of the structure shown in Fig. 1, is given by:

$C={\frac {\epsilon A}{t}}={\frac {\epsilon }{t}}\cdot w\cdot \ell =C_{\mathrm {layer} }\cdot w\cdot \ell$

(1)

Where $C_{\mathrm {layer} }={\tfrac {\epsilon }{t}}$ is the capacitance density of a particular layer, $\epsilon$ is the permittivity of the dielectric or insulating material, $t$ is the thickness of the dielectric, and $A=w\cdot \ell$ is the overlap area of the parallel-plate.

Parasitic Capacitances

In addition to the main parallel-plate capacitance, $C$, we would get the following parasitic capacitances:

• A bottom plate capacitance between the bottom plate and the substrate.
• fringing capacitances, due to the fringing electric fields between the:
  1. the top plate and bottom plate,
  2. the top plate and substrate, and
  3. bottom plate and substrate.