Difference between revisions of "220-A1.2"
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=== Simulating the RC Voltage Divider === | === Simulating the RC Voltage Divider === | ||
− | Let us start with the SPICE [https://github.com/louisalarcon/ee220/blob/master/src/wideband_voltage_divider.sp netlist] below, where we will analyze | + | Let us start with the SPICE [https://github.com/louisalarcon/ee220/blob/master/src/wideband_voltage_divider.sp netlist] below, where we will analyze it piece by piece. |
Line 1 is always reserved for the circuit title, and in this case, it is followed by a comment. The <code>.options</code> directive in line 4 instructs the simulator to save the device current data for later printing or plotting. | Line 1 is always reserved for the circuit title, and in this case, it is followed by a comment. The <code>.options</code> directive in line 4 instructs the simulator to save the device current data for later printing or plotting. | ||
Line 76: | Line 76: | ||
V1 in 0 dc 1 ac 1 pulse(-1 1 0 0.1u 0.1u 5u 0.01m) | V1 in 0 dc 1 ac 1 pulse(-1 1 0 0.1u 0.1u 5u 0.01m) | ||
+ | </source> | ||
+ | |||
+ | After describing the circuits we want to simulate, we then add a control block, which begins with the <code>.control</code> directive, and ends with the <code>.endc</code> directive. | ||
+ | |||
+ | <source lang="text" line start="29"> | ||
.control | .control | ||
Line 87: | Line 92: | ||
.endc | .endc | ||
+ | </source> | ||
+ | |||
+ | Finally, we end the netlist by the <code>.end</code> directive. | ||
+ | <source lang="text" line start="41"> | ||
.end | .end | ||
Revision as of 16:36, 7 August 2020
- Activity: Simulating simple RLC circuits
- At the end of this activity, the student should be able to:
- Run DC, AC, and transient simulations using ngspice.
Contents
A Wideband RC Voltage Divider
One way to build high-speed circuits with relatively large input impedances and capacitances is to use a simple RC voltage divider, as shown in the figure below. This RC divider is commonly found in oscilloscope 10X probes.
Let and similarly . Thus, the output voltage can be expressed as:
-
(1)
-
Notice that we can cancel out the pole with the zero when we set , or equivalently,
-
(2)
-
Intuitively, we can think if this as a resistive voltage divider at low frequencies, and a capacitive divider with the same ratio at high frequencies. Thus, the output voltage will simply be equal to:
-
(3)
-
We can then build a simple 10X oscilloscope probe circuit with an input impedance of and an input capacitance of using , , , and . Since the pole and zero cancel each other out, the bandwidth of the probe circuit is not limited by its RC values.
Let's look at the frequency response and transient response of this circuit using ngspice.
Simulating the RC Voltage Divider
Let us start with the SPICE netlist below, where we will analyze it piece by piece.
Line 1 is always reserved for the circuit title, and in this case, it is followed by a comment. The .options
directive in line 4 instructs the simulator to save the device current data for later printing or plotting.
1 * Wideband Voltage Divider Circuit
2 * LPA 05 Aug 2020
3
4 .options savecurrents
The next few lines describe our wideband voltage divider, composed of the resistors , , , and .
6 R1 in out 900k
7 R2 out 0 100k
8
9 C1 in out 1.1111p
10 C2 out 0 10p
To examine the effects of increasing the value of , we can add another circuit, but with .
12 * increase C1 and see what happens
13 R1a in outa 900k
14 R2a outa 0 100k
15
16 C1a in outa 1.6p
17 C2a outa 0 10p
Similarly, we can add yet another circuit with .
19 * decrease C1 and see what happens
20 R1b in outb 900k
21 R2b outb 0 100k
22
23 C1b in outb 0.7p
24 C2b outb 0 10p
We then add an input voltage, V1, that has a DC value of , an AC value (for our ac analysis later) also equal to , and during transient analysis, it will generate a square wave that goes from to , no time delay, a rise and fall time of , a pulse width of , and a period of .
26 * input square wave
27 V1 in 0 dc 1 ac 1 pulse(-1 1 0 0.1u 0.1u 5u 0.01m)
After describing the circuits we want to simulate, we then add a control block, which begins with the .control
directive, and ends with the .endc
directive.
29 .control
30
31 ac dec 10 1 1G
32 plot vdb(out) vdb(outa) vdb(outb)
33 wrdata testac.dat v(out) v(outa) v(outb)
34
35 tran 0.01u 0.03m
36 plot v(out) v(outa) v(outb)
37 wrdata testtran.dat v(out) v(outa) v(outb)
38
39 .endc
Finally, we end the netlist by the .end
directive.
41 .end
Notice that we described three copies of the same circuit, but with different values of . Lines 6-10 describe circuit 1, while lines 13-17 and 20-24 describe circuits 2 and 3 respectively, with the following values of : , , and . The three circuits all have the same ideal input voltage source, V1.