CoE 197U MOS Differential Pairs

The differential pair is one of the most commonly used circuit blocks in analog IC design. It enables amplifiers to have not just two, but specifically, differential inputs and act based only or mostly on the difference of the input signals.

The main references for this topic are chapters 3.5 and 4.3.5 of the Analysis and Design of Analog Integrated Circuits book.

Fully Differential Amplifier Signal and Gain Definitions

Before proceeding, the voltage signals to be dealt with need to be defined first to aid in the discussion. We will look at a general fully differential amplifier with a differential input and a differential output. The differential input/output voltages are the difference of input/output voltages. The common-mode input/output voltages are the average of the input/output voltages. Given how $v_{1}$, $v_{2}$, $v_{d}$, and $v_{d}$ are related (Fig. 1), knowledge of any two can be used to infer the remaining two.

Fig. 1Fully Differential Amplifier Voltage Definitions

Fig. 2 Fully Differential Amplifier Voltage Gain Definitions

Fig. 3 Cancellation of Common-mode Noise in Differential Signal

The presence of differential and common-mode inputs and outputs require a clarification on how the gains are defined (Fig. 2). An ideal fully differential amplifier will have a very large $A_{dm}$ and very low $A_{cm}$, as the arrows' thickness suggests. $A_{cm-dm}$ and $A_{dm-cm}$ are also ideally very low. $A_{cm-dm}$ and $A_{dm-cm}$ are both zero if the circuit is perfectly balanced, which requires that components are perfectly matched in terms of device properties and bias.

The advantage of having a differential input is the ability to reject signals that are common to both inputs such as noise that is coupled to both input signals. As can be seen in Fig. 3, the noise present on both inputs, $v_{1}$ and $v_{2}$, does not appear at the differential signal $v_{d}$. If indeed the differential pair works only on this differential input signal, then the noise will not be amplified with the actual input information. The same property also allows the circuit to be less sensitive to the DC offset of the two signals. This makes differential amplifiers easy to cascade without the need for AC-coupling capacitors, which generally need to be large and are costly in IC implementations. However, care is still needed when dealing with large signal swings and/or small supply voltages.

DC and Large Signal Analysis

The MOS differential pair or the source-coupled pair is shown in Figs. 4a and 4b. In source-coupled pairs, the source nodes are tied together. The current source is referred to as the tail current source. A simple but crude way of providing current to the differential pair is by using a tail resistor instead of a current source.

Figure 4a: MOS differential pair with tail current source bias

Figure 4b: MOS differential pair with tail resistor bias

Figure 5: MOS differential pair drain currents vs. differential input voltage

Assume that the transistors are perfectly matched/identical. Assume also that anything connected above the drain terminals are perfectly balanced or symmetric. For the DC analysis, assume that $\lambda \rightarrow 0$ for simplicity to highlight the basic operation of the circuit.

Consider the differential pair with a tail current source (Fig. 4a). When there is no differential input, then the input voltages $V_{I1}$ and $V_{I2}$ must exactly be equal at some common-mode voltage $V_{Ic}$. By virtue of symmetry, the transistors must have the same current, i.e. $I_{D1}=I_{D2}=I_{T}/2$. Such is the case without even taking note of what is the actual $V_{IC}$. If $V_{IC}$ should change, $V_{X}$ adjusts to maintain the Vgs that corresponds to $I_{D}=I_{T}/2$. Since $g_{m}$ can be inferred from the transistor dimensions and the DC current, which are both constant, then $g_{m}$ is maintained even if $V_{IC}$ changes, again, under the assumption that $\lambda \rightarrow 0$ or $r_{o}$ is very large.

The large signal characteristics of the MOS differential pair analysis is started by setting up a KVL equation from $V_{I1}$ to $V_{I2}$ and relating it to currents $I_{D1}$ and $I_{D1}$, under the restriction that $I_{D1}+I_{D2}=I_{T}$. The following equations are valid given that the two transistors are saturated.

For $|V_{id}|<V_{id,max}={\sqrt {\frac {2I_{T}}{k'{\frac {W}{L}}}}}$:

$I_{D1}={\frac {I_{T}}{2}}+{\frac {k'}{4}}{\frac {W}{L}}V_{id}{\sqrt {{\frac {4I_{T}}{k'{\frac {W}{L}}}}-V_{id}^{2}}}$

(1)

$I_{D2}={\frac {I_{T}}{2}}-{\frac {k'}{4}}{\frac {W}{L}}V_{id}{\sqrt {{\frac {4I_{T}}{k'{\frac {W}{L}}}}-V_{id}^{2}}}$

(2)

When $|V_{id}|>V_{id,max}$, all of $I_{T}$ will flow only through one transistor while the other transistor will be in cut-off. This is shown in Fig. 5. Thus, the tail current is effectively steered or distributed between M1 and M2 by $V_{id}$, regardless of the $V_{ic}$ as long as the transistors are saturated and the current source is still operating as intended.

Figure 6: MOS differential pair with resistor load

Figure 7: Vod vs. Vid of differential amplifier with resistor load

Assuming that the load is a pair of equal and matched resistors such in Fig. 6, the output voltage is determined by KVL (Eq. 3) and the difference in drain currents (Eqs. 1 and 2). The resulting expression is Eq. 4. The plot of this function is the middle portion of Fig. 7.

$V_{od}=V_{o1}-V_{o2}=(V_{CC}-I_{D1}R_{D})-(V_{CC}-I_{D2}R_{D})$

(3)

For $|V_{id}|<V_{id,max}$:

$V_{od}=-R_{D}{\frac {k'}{2}}{\frac {W}{L}}V_{id}{\sqrt {{\frac {4I_{T}}{k'{\frac {W}{L}}}}-V_{id}^{2}}}$

(4)

Beyond $|V_{id,max}|$ the currents rail, and therefore, the differential output voltage also rail. Fig. 7 also shows that the amplifier has an inverting gain.

Small-Signal AC and Half Circuit Analysis

Taking the limit as , it can be shown that the $v_{od}(v_{id})$ approaches a linear function, and the small-signal gain is $-g_{m}R_{D}$ which must be very familiar. Note that this $g_{m}$ is evaluated at the case where $V_{id}$ is around 0, where $I_{D1}\approx I_{D2}\approx {\frac {I_{T}}{2}}$, and that the small-signal gain represents the slope of the $V_{od}$ vs. $V_{id}$ plot for very small $V_{id}$. The expression is not very accurate because Eqs. 4 and 5 assumes that $r_{o}$ is very large.

$A_{dm}={\frac {v_{od}}{v_{id}}}=\left.{\frac {\partial V_{od}}{\partial V_{id}}}\right|_{V_{id}\rightarrow 0}$

$A_{dm}\approx -R_{D}{\frac {k'}{2}}{\frac {W}{L}}{\sqrt {\frac {4I_{T}}{k'{\frac {W}{L}}}}}$

$A_{dm}\approx -R_{D}{\sqrt {2k'{\frac {W}{L}}\left({\frac {I_{T}}{2}}\right)}}=-R_{D}{\sqrt {2k'{\frac {W}{L}}I_{D1}}}=-R_{D}{\sqrt {2k'{\frac {W}{L}}I_{D2}}}=-g_{m}R_{D}$

(5)

Eq. 5 shows that the small-signal differential gain is dependent only on Rd, the transistor dimensions, and the tail current. Changing the DC bias of the input voltage will not affect the gain as long as the transistors are saturated and the tail current is fixed.

Analyzing the circuit’s small-signal model will help determine the small-signal gains easier, without having to assume that $r_{o}\rightarrow \infty$. The full small-signal equivalent circuit is shown in Fig. 8. Here we are assuming that the tail current source is non-ideal and has some finite small-signal resistance $r_{tail}$. Note also, that transistors’ $r_{o}$ are maintained.

Figure 8: Small-signal equivalent circuit of the MOS differential amplifier with resistor load

The differential gain $A_{dm}$ is analyzed with $v_{ic}=0$. If the circuit is perfectly balanced, it follows that $v_{oc}=0$. Due to symmetry, analyzing only half of the circuit should already give us enough information. With differential inputs only in play, one side/half can be considered “positive” while the other side/half can be considered “negative.” Thus, the middle point/s of the differential circuit must be at small-signal 0V. We can divide the circuit in half and place a virtual differential ground at each wire that is cut by the axis of symmetry. Note, however, that we must still maintain the voltage definitions with $v_{ic}=0$ (i.e. $v_{i1}$ remains $+{\frac {v_{id}}{2}}$, etc.) as in Fig. 9.

Figure 9: Determining the differential half circuit

Figure 10: Differential half circuit of the differential pair with resistor load

Taking the left-side of Fig. 8 for the differential half circuit analysis, we end up with Fig. 10. Note that the voltages are still $+{\frac {v_{id}}{2}}$ and $+{\frac {v_{od}}{2}}$. The tail resistance was also divided into two $2\cdot r_{tail}$’s to properly cut the circuit in half. The source is at (differential) ground, and thus, $r_{tail}$ is effectively shorted. The remaining portion of the half circuit resembles that of a resistor-loaded common source, whose gain is $-g_{m}\left(r_{o}||R_{D}\right)$. However, the input is ${\frac {v_{id}}{2}}$ while the output is ${\frac {v_{od}}{2}}$. Thus, this gain is given by:

${\frac {v_{od}/2}{v_{id}/2}}=-g_{m}\left(r_{o}||R_{L}\right)$

$A_{dm}={\frac {v_{od}}{v_{id}}}=-g_{m}\left(r_{o}||R_{L}\right)$

(6)

For the common-mode case, $v_{id}$ must be set to zero which consequently makes $v_{od}=0$. This time, since we are applying common or the same excitation on both sides of a balanced circuit then, there must be no current flowing either from left to right or from right to left since the two sides are at the same potential. Thus, portions that are cut in dividing the circuit into two are left open, instead of placing a ground, as shown in Fig. 11. The common-mode half circuit is shown in Fig. 12. This circuit follows the same structure as a common source amplifier with emitter degeneration, and with $R_{C}=R_{L}$ and $R_{E}=2r_{tail}$. The gain of such a circuit is approximately ${\frac {-g_{m}R_{C}}{1+g_{m}R_{E}}}$. Thus, the common-mode gain is given by Eq. 7. Note that if the current source were ideal, then $r_{tail}\rightarrow \infty$ and $A_{cm}\rightarrow 0$.

$A_{cm}\approx {\frac {v_{oc}}{v_{ic}}}=-{\frac {g_{m}R_{L}}{1+g_{m}\cdot 2r_{tail}}}$

(7)

Figure 11: Determining the common-mode half circuit

Figure 12: Common-mode half circuit of the differential pair with resistor load

Note that the previous expression is valid only when there is no body effect. However, this is not true for the circuit in Fig. 6 since the body is grounded while the source is not. In a standard CMOS technology with a p-type substrate, shorting the PMOS source to its body is easy since each PMOS has its own n-well. However, for NMOS, the body is also the substrate that is shared across the whole chip. It will only be possible to short the NMOS source to the body, without shorting the rest of the substrate, if the technology has a way to isolate and tap an NMOS’s p-type body from the rest of the chip. Such a feat is possible with a triple well technology (Fig. 13).

Figure 13: Transistors in a triple-well technology

If the body is not or cannot be tied to the source, then the body effect occurs, where changes in $v_{BS}$ cause threshold voltage to change. Thus, when the source potential changes, the drain current changes not only because $v_{GS}$ changes but also because the threshold voltage changes. The small-signal common-mode half circuit with the body effect is shown in Fig. 14. Analysis of this half circuit will lead to a common-mode gain expressed by Eq. 8. Note that the body transconductance is given by $g_{mb}=\chi g_{m}$

$A_{cm}\approx -{\frac {g_{m}}{1+g_{m}\left(1+\chi \right)\cdot 2r_{tail}}}\cdot R_{L}||\left(r_{o}+2r_{tail}+g_{m}\left(1+\chi \right)r_{o}\cdot 2r_{tail}\right)$

(8)

$A_{cm}\approx -{\frac {g_{m}R_{L}}{1+g_{m}\left(1+\chi \right)\cdot 2r_{tail}}}$

Figure 14: Common-mode half circuit of the resistor-loaded differential pair with body effect

Note that there is no body effect in the differential circuit even if the source not shorted to the body since the bulk is grounded and the source is at the differential ground. Thus, the small-signal $v_{bs}$ is 0.

CMRR

$CMRR=\left|{\frac {A_{dm}}{A_{cm}}}\right|$

(9)

The common-mode rejection ratio or CMRR is given by Eq. 9. CMRR is a primary figure of merit for differential amplifiers. The higher the CMRR, the better. For the differential pair with body effect, the CMRR is approximately given by Eq. 10. The CMRR of the differential amplifier improves with increasing $r_{tail}$ and is independent of the load resistance. The equation also shows that the body effect helps improve CMRR since χ is a positive quantity typically around 0.1 to 0.3. Although the body-effect improves CMRR by reducing Acm, it must be noted that the body effect still influences the threshold voltage and can impact the allowable DC voltage levels and signal swing.

$CMRR\approx 1+g_{m}\left(1+\chi \right)\cdot 2r_{tail}$

(10)

Eq. 10 can be expressed in terms of the transistor currents and overdrive voltage. Assuming that the tail current source is some NMOS transistor biased at saturation, then the tail resistance must be some $r_{o}$, and the expressions below can be obtained. The equations show that to improve CMRR, the length of the tail current source transistor must be increased (to decrease $\lambda _{T}$) while the overdrive of the differential pair must be decreased (larger width-length ratio for the same current).

$CMRR\approx 1+{\frac {2I_{D1}}{V_{OV1}}}\left(1+\chi \right)\cdot 2\left({\frac {1}{\lambda _{T}I_{T}}}\right)$

$CMRR\approx 1+{\frac {2\left(1+\chi \right)}{V_{OV1}\cdot \lambda _{T}}}$

Differential Pair with Active Load

Larger gains can be achieved when using active loads. Fig. 15 shows an active-loaded differential pair. The two load transistors act like current sources. M3 and M4 must be biased such that $I_{D3}=I_{D4}={\frac {I_{T}}{2}}$ at DC.

At AC, the gates of M3 and M4 are grounded since Vbias is some constant voltage bias or reference. Aside from that, the gates of M3 and M4 are at differential ground. Thus, at AC, M3 and M4 simply present a resistance $r_{op}$, and the differential gain must be

$A_{dm}=-g_{mn}\left(r_{on}\parallel r_{op}\right)$

Figure 15: Differential pair with active load and the equivalent circuit for small-signal analysis

Although the gain of this circuit is larger compared to the resistor-loaded case, maintaining the correct DC operation is harder. Even a minor mismatch between $I_{D3}$, $I_{D4}$, and ${\frac {I_{T}}{2}}$ will cause the output nodes to rail up or down, putting the load transistors or the differential pair in the linear region, respectively. Also, note that the output DC voltage is not well-defined unlike in the resistor-loaded case where $v_{o1,2}$ can be easily found to be $V_{DD}-I_{D1,2}R_{L}$. Some form of common-mode feedback or CMFB is necessary to ensure that the active-loaded differential pair will have a stable DC output level and to ensure that transistors are saturated.