CoE 197U The CMOS Inverter

To understand the analysis and design of digital circuits, we will look at its fundamental element -- the digital gate. We will start with the simplest digital gate, the inverter.

The Inverter Voltage Transfer Characteristics (VTC)

The functionality of the inverter can be captured by looking at the output voltage as we change the input voltage, or the voltage-transfer characteristic (VTC).

The Ideal Inverter VTC

Let us define an ideal inverter, where:

$v_{O}={\begin{cases}V_{H},&{\text{if }}v_{I}<V_{REF}\\V_{L},&{\text{if }}v_{I}\geq V_{REF}\end{cases}}$

(1)

Where $V_{H}$ is logic 1 voltage level, and in general may or may not be equal to the positive supply voltage, $V_{+}$, and $V_{L}$ is logic 0 voltage level, and in general may or may not be equal to the negative supply voltage, $V_{-}$. The VTC of this ideal inverter, as well as the standard inverter circuit symbol, is shown in Fig. 1.

Figure 1: The ideal inverter voltage transfer characteristic (VTC).

Inverter Implementations

One implementation of the inverter is to use a single NMOS transistor and a resistor, as shown in Fig. 2. Using our switch model for the NMOS transistor, we can see that when the input is low or at logic 0, the output is pulled up to $V_{DD}$ since the switch is open. When the input voltage is equal to $V_{DD}>V_{TH}$, the switch is closed and the output is pulled down close to ground. For a finite on switch resistance, $R_{ON}$, the output voltage becomes:

$v_{O}={\frac {R_{ON}}{R_{ON}+R}}\cdot V_{DD}$

(2)

Note that a finite $R_{ON}$ will degrade (increase) low output voltage or logic 0 level. Additionally, the when the output of the NMOS inverter is low, there is a non-zero current flowing through the resistor, resulting in static power consumption, or power consumed from the supply even when there is no switching activity present in the circuit.

Figure 2: The NMOS inverter.

Figure 3: The CMOS inverter.

Another implementation of the inverter is to use an NMOS and a PMOS transistor. This complementary (CMOS) configuration turns on only one switch at a time since the gates of the two transistors are connected to each other. Thus, an input voltage of $V_{DD}>V_{TH}$ will turn on (close) the NMOS switch, and turn off (open) the PMOS switch since the gate-to-source voltage of the PMOS transistor is zero, pulling the inverter output down to ground. When the input voltage is ground or logic 0, the NMOS switch is open and the PMOS is closed, pulling the output up to $V_{DD}$.

Note that due to the complementary function of the CMOS inverter, there is no static current flowing when the output is either at logic 0 or logic 1. However, current will flow during the transition from 0$\rightarrow$1 or 1$\rightarrow$0.

We can derive the VTC of any inverter by determining the regions of operation of each transistor as we vary the input voltage. Fig. 4 shows the VTC of the CMOS inverter with the corresponding regions of operation, which are dependent on the input and output voltages. Note that:

• $v_{GS,{\text{n}}}=v_{I}$
• $v_{GS,{\text{p}}}=V_{DD}-v_{I}$
• $v_{DS,{\text{n}}}=v_{O}$
• $v_{DS,{\text{p}}}=V_{DD}-v_{O}$.

Figure 4: The CMOS inverter voltage transfer characteristic (VTC).

Static Design Metrics

The general form of the inverter voltage transfer characteristic is shown in Fig. 5. We can define several metrics to enable us to determine how close the real VTC is to the ideal VTC.

Figure 5: The non-ideal inverter voltage transfer characteristic (VTC).

Figure 6: Cascaded inverters.

Consider the cascaded inverter in Fig. 6:

• $V_{H}$ is the output high or logic 1 output of the inverter, and is seen at the output when $V_{L}$ or logic 0 is placed at the input of the inverter.
• $V_{L}$ is the output low or logic 0 output of the inverter, and is seen at the output when $V_{H}$ or logic 1 is placed at the input of the inverter.

In the ideal inverter VTC in Fig. 1, we see that we have two flat regions (zero gain) and a vertical region (infinite gain). However, in a non-ideal VTC, the zero gain regions degrade into low gain regions where the absolute value of the slope is typically less than 1, and a high-gain region where the absolute value of the slope is greater than 1. The boundaries between the high- and low-gain regions are marked by the points where the absolute value of the slope of the VTC is equal to 1.

The two points with a slope of $-1$ are shown in Fig. 5 and are located at the following coordinates:

• ($V_{IL},V_{OH}$)
• ($V_{IH},V_{OL}$)

Where $V_{IL}$ is the highest input voltage the inverter will still consider as a low voltage. Anything above this places the inverter in the high-gain region of the VTC, making it sensitive to noise and interference. Similarly, $V_{IH}$ is the lowest input voltage the inverter will still consider as a high voltage.

Noise in Digital Circuits

One of the main advantages of digital circuits over analog circuits is its relatively good noise immunity. In a binary digital logic system, we reduce the amount of information carried by a digital signal to just 1 bit. This then increases the digital circuit's resiliency to interference noise from nearby signals, or from inherent device noise. The zero-gain regions of the ideal inverter VTC are ideal at the points near $V_{H}$ and $V_{L}$ since any disturbance nor noise added to the input voltage would just be ignored by the inverter, i.e. the output voltage will not change.

Noise Margins

To quantify this robustness to noise and interference, we define the following metrics:

• $NM_{H}=V_{OH}-V_{IH}$ is the noise margin at the high output level, and is the maximum noise that can degrade the input high or logic 1 level to the point where the inverter might not recognize it as a high level anymore.
• $NM_{L}=V_{IL}-V_{OL}$ is the noise margin at the low output level, and is the maximum noise that can degrade the input low or logic 0 level to the point where the inverter might not recognize it as a low level anymore.

Inverter Delay

Figure: Logic delay definitions .

Power Dissipation

Figure : The CMOS switching current.

Figure : The CMOS transient power dissipation.