Difference between revisions of "CoE 197U The MOS Switch"

From Microlab Classes
Jump to navigation Jump to search
Line 13: Line 13:
  
 
=== The Ideal Switch ===
 
=== The Ideal Switch ===
 +
 +
{|
 +
|[[File:Ideal switch.svg|thumb|400px|Figure 4: The ideal switch V-I characteristics.]]
 +
|-
 +
|}
  
 
=== The Switch Model of a Transistor ===
 
=== The Switch Model of a Transistor ===

Revision as of 17:52, 4 March 2021

Levels of Abstraction

Figure 1: Levels of abstraction[1].

What is a Transistor?

Figure 2: The 45nm NMOS PTM[2] output characteristics.

The Ideal Switch

Figure 4: The ideal switch V-I characteristics.

The Switch Model of a Transistor

NMOS vs. PMOS Transistors

References

  1. A. Ghosh, Fault Modeling in Chip Design - VLSI DFT, 2020 (link)
  2. Arizona State University Predictive Technology Models (PTM) website