CoE 197U CMOS Gates

In this lecture, we will cover the following:

• Review of combinational logic
• CMOS gate sizing
• Designing for speed

Use the provided slide deck to guide you through this discussion. The main reference for this lecture is Chapter 6 of the Digital IC book.

Combinational Logic Review

Combinational logic funstions are functions whose output value/s depend only on the current input values. They are typically expressed as Boolean functions, truth tables or logic gate networks. Common logic gates used are inverters (as discussed in previous lecture), AND gates, NAND gates, OR gates, NOR gates, etc. Static complementary gates are implemented using complementary (or dual) networks: a pull-up network (PUN) composed of PMOS transistors and a pull-down network (PDN) composed of NMOS transistors. The simplest of these gates is the inverter, where the PUN is a single PMOS and the PDN is a single NMOS, as shown in figure 1. Slide 5 also shows the corresponding layout (middle figure) and stick diagram (right figure) of an inverter.

CMOS Logic Gates

To design these logic gates, we can treat the transistors as controlled switches, similar to how we analyzed the inverter. We recall that NMOS switch closes when the control is HIGH, while PMOS switch closes when the control input is LOW. Connecting them in series or in parallel performs the logic as shown in figure 2.