Difference between revisions of "CoE 197U CMOS Gates"
Jump to navigation
Jump to search
(Created page with "In this lecture, we will cover the following: * Review of combinational logic * CMOS gate sizing * Designing for speed") |
|||
| Line 3: | Line 3: | ||
* CMOS gate sizing | * CMOS gate sizing | ||
* Designing for speed | * Designing for speed | ||
| + | |||
| + | Use the provided slide deck to guide you through this discussion. | ||
| + | The main reference for this lecture is '''Chapter 6''' of the Digital IC book. | ||
| + | |||
| + | == Combinational Logic Review == | ||
| + | Combinational logic funstions are functions whose output value/s depend only on the current input values. They are typically expressed as Boolean functions, truth tables or logic gate networks. Common logic gates used are inverters (as discussed in previous lecture), AND gates, NAND gates, OR gates, NOR gates, etc. '''Static complementary gates''' are implemented using complementary (or dual) networks: a ''pull-up network (PUN)'' composed of PMOS transistors and a ''pull-down network (PDN)'' composed of NMOS transistors. | ||
Revision as of 18:25, 22 February 2021
In this lecture, we will cover the following:
- Review of combinational logic
- CMOS gate sizing
- Designing for speed
Use the provided slide deck to guide you through this discussion. The main reference for this lecture is Chapter 6 of the Digital IC book.
Combinational Logic Review
Combinational logic funstions are functions whose output value/s depend only on the current input values. They are typically expressed as Boolean functions, truth tables or logic gate networks. Common logic gates used are inverters (as discussed in previous lecture), AND gates, NAND gates, OR gates, NOR gates, etc. Static complementary gates are implemented using complementary (or dual) networks: a pull-up network (PUN) composed of PMOS transistors and a pull-down network (PDN) composed of NMOS transistors.
