Difference between revisions of "CoE 197U"
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* Design multistage networks for optimal speed | * Design multistage networks for optimal speed | ||
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+ | * Slides: CMOS Gates [https://drive.google.com/file/d/1Ohu6h00q8o3mN6PfKG0_ArZ7F97qvOji/view?usp=sharing PDF] | ||
+ | * Slides: Logical Effort [https://drive.google.com/file/d/1OmX857DUfy0X_asE1DKYCIrr9TwwMMvX/view?usp=sharing PDF] | ||
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* Model interconnects as parasitic resistances and capacitances and estimate corresponding delay | * Model interconnects as parasitic resistances and capacitances and estimate corresponding delay | ||
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+ | * Slides: Power and Energy [https://drive.google.com/file/d/1OpKOIEaYL6B4tIJ4WBeFDanvIL5H-3RE/view?usp=sharing PDF] | ||
+ | * Slides: Interconnects [https://drive.google.com/file/d/1Or0KnHb3v0awBcXZHd8CfN2oEP5l3cRj/view?usp=sharing PDF] | ||
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Revision as of 14:16, 22 February 2021
- Introduction to Analog and Digital Integrated Circuit Design
- Semester Offered: 2nd semester
- Course Credit: Lecture: 3 units (2 units lecture, 1 unit lab)
Catalog Description
IC Fabrication. CMOS gates. Logical Effort. Interconnect. Memory Elements. MOS Amplifiers. Current Sources. Differential Amplifiers. Operational Transconductance Amplifiers. Pre-req: EEE 41 or EEE 131. 5h (2 lec, 3 lab) 3 u.
Syllabus
Module | Topics | Outcomes | Resources | Activities |
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Part I: Digital Integrated Circuits | ||||
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Part II: Analog Integrated Circuits | ||||
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References
- Rabaey, Chandrakasan, Nikolic, Digital Integrated Circuits, 2ed., Pearson 2002.
- Gray, Hurst, Lewis, Meyer, Analysis & Design of Analog Integrated Circuits, Wiley 2001.
- Johns, Martin, Analog Integrated Circuit Design, Wiley 1997.
- Design of Analog CMOS Integrated Circuits, Behzad Razavi, McGraw-Hill, 2000.