CMOS Technology and Fabrication

Welcome to EE 220!

Since we are offering this class remotely, there will be many changes to our normal course delivery:

1. There will be no face-to-face lecture classes. All the material will be made available via this site.
2. There will be more emphasis on student-centric activities, e.g. analysis, design, and simulations. Thus, you will be mostly "learning by doing". In this context, we will set aside an hour every week for consultations and questions via video-conferencing.
3. Grades will be based on the submitted deliverables from the activities. Though we will not be very strict regarding the deadlines, it is a good idea to keep up with the class schedule and avoid cramming later in the semester.

Please remember that this semester is very different from those before, and please make sure you inform me if you have any issues or difficulties regarding the class. Also, keep in mind that you will need to pay a bit more attention to your time management as it will play a critical role during the course of the semester.

Let's get started!

CMOS Technology Review

Knowing how integrated devices are fabricated, and how the fabrication process affects the characteristics and performance of these devices, is one of the pillars of good analog circuit design. In analog design, we are interested in the relationships between the fabrication process steps and parameters to the device characteristics and performance.

However, most advances in CMOS fabrication processes are, most of the time, driven by the performance requirements of digital circuits. As we can see in Figs. 1-3, scaling offers significant improvement in device area, speed, and power consumption.

Figure 1: Area improvement.

Figure 2: Delay improvement.

Figure 3: Power consumption.

In many cases, this reduction in delay, which translates to increased clock frequencies, it not really realized, due to the increased heat dissipation requirements at high clock frequencies, since $P_{\mathrm {digital} }=\alpha \cdot C_{\mathrm {eff} }\cdot V_{DD}^{2}\cdot f$, where $\alpha$ is the activity factor of a digital circuit, $C_{\mathrm {eff} }$ is the effective capacitance being driven, $V_{DD}$ is the supply voltage, and $f$ is the clock frequency. This is evident in Fig. 4, where even though the transistor count increases due to scaling, the power limits the further increase in clock frequencies. Thus, in order to increase performance, designers use "More than Moore" techniques such as parallelism.

Figure 4: Scaling and processor performance.

Figure 5: Supply and threshold voltage scaling.

One way to reduce the power consumption of digital circuits is to reduce the supply voltage, as seen in Fig. 5. In many ways, as we will see during the semester, reducing the supply voltage makes analog design harder by (1) reducing the signal-to-noise ratios, and (2) increasing the effect of variability as illustrated in Fig. 6. The task of the analog designer, therefore, is to design circuits that operate reliably in the face of the various constraints imposed by the fabrication process.

Figure 6: Reducing $V_{DD}$: Analog vs. Digital

Sources

• Phillip Allen's slides on CMOS fabrication.