Difference between revisions of "220-A1.1"
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(Created page with "* Activity: '''IC Fabrication''' * '''Instructions:''' In this activity, you are tasked to ** Watch a short video about integrated circuit (IC) fabrication. ** Read a paper...") |
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* T. Skotnicki, J. A. Hutchby, Tsu-Jae King, H. -. P. Wong and F. Boeuf, '''The end of CMOS scaling: toward the introduction of new materials and structural changes to improve MOSFET performance,''' in ''IEEE Circuits and Devices Magazine'', vol. 21, no. 1, pp. 16-26, Jan.-Feb. 2005, doi: 10.1109/MCD.2005.1388765. | * T. Skotnicki, J. A. Hutchby, Tsu-Jae King, H. -. P. Wong and F. Boeuf, '''The end of CMOS scaling: toward the introduction of new materials and structural changes to improve MOSFET performance,''' in ''IEEE Circuits and Devices Magazine'', vol. 21, no. 1, pp. 16-26, Jan.-Feb. 2005, doi: 10.1109/MCD.2005.1388765. | ||
** You can access this paper for free via the UPEEEI VPN service. If you cannot access the IEEE link via the UPEEEI VPN, you can also access this via this [https://inst.cs.berkeley.edu/~n241/sp07/index_files/The%20end%20of%20CMOS%20scaling.pdf link]. | ** You can access this paper for free via the UPEEEI VPN service. If you cannot access the IEEE link via the UPEEEI VPN, you can also access this via this [https://inst.cs.berkeley.edu/~n241/sp07/index_files/The%20end%20of%20CMOS%20scaling.pdf link]. | ||
| + | * S. Taranovich, '''Analog: back to the future''', ''EDN Online'', ([https://www.edn.com/analog-back-to-the-future-part-one/ part 1],[https://www.edn.com/analog-back-to-the-future-part-two/ part 2], [https://www.edn.com/analog-back-to-the-future-part-3/ part 3]) | ||
=== VPN Access === | === VPN Access === | ||
For questions on UPEEEI VPN access, please send an email to EEEI Support: <math>\mathrm{support}</math>@<math>\mathrm{eee.upd.edu.ph}</math> | For questions on UPEEEI VPN access, please send an email to EEEI Support: <math>\mathrm{support}</math>@<math>\mathrm{eee.upd.edu.ph}</math> | ||
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== Report Guide == | == Report Guide == | ||
Revision as of 17:01, 11 September 2020
- Activity: IC Fabrication
- Instructions: In this activity, you are tasked to
- Watch a short video about integrated circuit (IC) fabrication.
- Read a paper on CMOS scaling, and an article on the history of analog design.
- Write a short (1-page) report.
- Should you have any questions, clarifications, or issues, please contact your instructor as soon as possible.
- At the end of this activity, the student should be able to:
- Enumerate and explain the key steps and technologies involved in fabricating integrated circuits.
- Explain why there is a concern about the future of CMOS technology.
Video
- Video: Silicon Run I (1996) Youtube link
Paper/Article Reading
- T. Skotnicki, J. A. Hutchby, Tsu-Jae King, H. -. P. Wong and F. Boeuf, The end of CMOS scaling: toward the introduction of new materials and structural changes to improve MOSFET performance, in IEEE Circuits and Devices Magazine, vol. 21, no. 1, pp. 16-26, Jan.-Feb. 2005, doi: 10.1109/MCD.2005.1388765.
- You can access this paper for free via the UPEEEI VPN service. If you cannot access the IEEE link via the UPEEEI VPN, you can also access this via this link.
- S. Taranovich, Analog: back to the future, EDN Online, (part 1,part 2, part 3)
VPN Access
For questions on UPEEEI VPN access, please send an email to EEEI Support: @
Report Guide
Based on the video you watched, the papers (not limited to the two papers above) you have read, and any other resource that is available to you, write a short (1-2 page) report on what you think would be the key challenges IC designers will face in the near future, and why.
Submission
Submit your reports via email, before starting Module 2.
