Difference between revisions of "CoE197U-A1.1"
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** Read Gordon Moore's 1965 paper. | ** Read Gordon Moore's 1965 paper. | ||
** Read a paper on CMOS scaling. | ** Read a paper on CMOS scaling. | ||
− | ** Read a paper on | + | ** Read a paper on process variability. |
** Write a short (1-page) report. | ** Write a short (1-page) report. | ||
* Should you have any questions, clarifications, or issues, please contact your instructor as soon as possible. | * Should you have any questions, clarifications, or issues, please contact your instructor as soon as possible. |
Revision as of 17:22, 26 February 2021
- Activity: IC Fabrication and Scaling
- Instructions: In this activity, you are tasked to
- Watch a short video about integrated circuit (IC) fabrication.
- Read Gordon Moore's 1965 paper.
- Read a paper on CMOS scaling.
- Read a paper on process variability.
- Write a short (1-page) report.
- Should you have any questions, clarifications, or issues, please contact your instructor as soon as possible.
- At the end of this activity, the student should be able to:
- Enumerate and explain the key steps and technologies involved in fabricating integrated circuits.
- Explain why there is a concern about the future of CMOS technology.
Video
- Video: Silicon Run I (1996) Youtube link
After watching the video, go over Phillip Allen's slides on CMOS fabrication. This is a good simplified overview of the modern IC fabrication process.
Paper/Article Reading
- Gordon E Moore, Cramming more components onto integrated circuits, Electronics, Volume 38, Number 8, April 19, 1965 (pdf)
- T. Skotnicki, J. A. Hutchby, Tsu-Jae King, H. -. P. Wong and F. Boeuf, The end of CMOS scaling: toward the introduction of new materials and structural changes to improve MOSFET performance, in IEEE Circuits and Devices Magazine, vol. 21, no. 1, pp. 16-26, Jan.-Feb. 2005, doi: 10.1109/MCD.2005.1388765.
- S. Borkar, Designing reliable systems from unreliable components: the challenges of transistor variability and degradation, in IEEE Micro, vol. 25, no. 6, pp. 10-16, Nov.-Dec. 2005, doi: 10.1109/MM.2005.110.
- You can access this paper for free via the UPEEEI VPN service.
- IEEExplore link.
VPN Access
For questions on UPEEEI VPN access, please send an email to EEEI Support: @
Report Guide
Based on the video you watched, the papers (not limited to the papers above) you have read, and any other resource that is available to you, write a short (1-2 page) report on what you think would be the key challenges IC designers will face in the near future, and why.
Submission
Submit your report via email before starting Module 2.