Integrated Capacitors

Similar to resistors, in a CMOS process optimized for digital circuits, capacitances are treated as parasitic devices that degrade the performance of digital circuits, except in specialized cases such as memory circuits. However, in analog design, we often need capacitors with very well-controlled capacitance values.

Capacitance Geometries

Figure 1: A parallel-plate capacitance.

The parallel-plate capacitance of the structure shown in Fig. 1, is given by:

$C={\frac {\epsilon A}{t}}={\frac {\epsilon }{t}}\cdot w\cdot \ell =C_{\mathrm {layer} }\cdot w\cdot \ell$

(1)

Where $C_{\mathrm {layer} }={\tfrac {\epsilon }{t}}$ is the capacitance density of a particular layer, $\epsilon$ is the permittivity of the dielectric or insulating material, $t$ is the thickness of the dielectric, and $A=w\cdot \ell$ is the overlap area of the parallel-plate.

Parasitic Capacitances

In addition to the main parallel-plate capacitance, $C$, we would get the following parasitic capacitances:

• A bottom plate parasitic capacitance, $C_{\mathrm {bottom} }$, between the bottom plate and the substrate.
• Perimeter-dependent fringing capacitances, due to the fringing electric fields between the:
  1. top plate and bottom plate, $C_{1}$, resulting in an increase in the main capacitance predicted by the parallel-plate expression in Eq. 1,
  2. top plate and substrate, $C_{2}$, adding a top plate parasitic capacitance, and
  3. bottom plate and substrate, $C_{3}$, again adding to the capacitance predicted by our parallel-plate formula.

Note that it is much harder to model and predict the capacitance due to the non-uniform fringing electric fields. We can reduce the effects of the fringing fields by making the main capacitance much larger than the parasitic fringing capacitances by minimizing the perimeter of the parallel-plate structure.