Difference between revisions of "CoE197U-A3.1"
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| − | Slide 28 of the CMOS Gates slide set shows 3 possible implementation of an 8-input AND gate. Using the techniques you learned from logical effort, and assuming a 3:1 reference inverter, determine which of these 3 implementations is the fastest. Then determine the proper sizes of the gates for the fastest implementation. | + | Slide 28 of the CMOS Gates slide set shows 3 possible implementation of an 8-input AND gate. Each input may have a maximum input capacitance equal to twice that of a minimum sized 3:1 inverter. The AND gate needs to drive a load 100 times the input capacitance of a minimum sized 3:1 inverter (i.e. <math> H = \frac{100}{2} </math>). Using the techniques you learned from logical effort, and assuming a 3:1 reference inverter, determine which of these 3 implementations is the fastest. Then determine the proper sizes of the gates for the fastest implementation. |
Latest revision as of 10:18, 12 March 2022
- Topic: Logical Effort
- Instructions:
- Go over the supplied slide deck on logical effort. Go through the given sample problems to ensure you understood the process.
- Show complete solution, write assumption (if any), explain each step
- All answers should be in a single pdf file with the following naming convention: CoE197U-A3_1-<family_name>-<first_name>.pdf
- Submit your answer in the UVLe submission bin (Logic Gates tile, Logical Effort Submission Bin)
Question: Slide 28 of the CMOS Gates slide set shows 3 possible implementation of an 8-input AND gate. Each input may have a maximum input capacitance equal to twice that of a minimum sized 3:1 inverter. The AND gate needs to drive a load 100 times the input capacitance of a minimum sized 3:1 inverter (i.e. ). Using the techniques you learned from logical effort, and assuming a 3:1 reference inverter, determine which of these 3 implementations is the fastest. Then determine the proper sizes of the gates for the fastest implementation.
