220-A1.2

• Activity: Simulating simple RLC circuits
• At the end of this activity, the student should be able to:

1. Run DC, AC, and transient simulations using ngspice.

A Wideband RC Voltage Divider

One way to build high-speed circuits with relatively large input impedances and capacitances is to use a simple RC voltage divider, as shown in the figure below. This RC divider is commonly found in oscilloscope 10X probes.

Figure 1: A wideband voltage divider circuit.

Let $Z_{1}=R_{1}\|{\frac {1}{sC_{1}}}={\frac {R_{1}}{1+sR_{1}C_{1}}}$ and similarly $Z_{2}={\frac {R_{2}}{1+sR_{2}C_{2}}}$. Thus, the output voltage can be expressed as:

$v_{out}={\frac {Z_{2}}{Z_{1}+Z_{2}}}\cdot v_{in}={\frac {R_{2}}{R_{1}+R_{2}}}\cdot {\frac {1+sR_{1}C_{1}}{1+s{\frac {R_{1}R_{2}}{R_{1}+R_{2}}}\left(C_{1}+C_{2}\right)}}\cdot v_{in}={\frac {R_{2}}{R_{1}+R_{2}}}\cdot {\frac {1+{\frac {s}{\omega _{z}}}}{1+{\frac {s}{\omega _{p}}}}}\cdot v_{in}$

(1)

Notice that we can cancel out the pole with the zero when we set $\omega _{z}=\omega _{p}$, or equivalently,

${\frac {C_{1}}{C_{1}+C_{2}}}={\frac {R_{2}}{R_{1}+R_{2}}}$

(2)

Intuitively, we can think if this as a resistive voltage divider at low frequencies, and a capacitive divider with the same ratio at high frequencies. Thus, the output voltage will simply be equal to:

$v_{out}={\frac {R_{2}}{R_{1}+R_{2}}}\cdot v_{in}$

(3)

We can then build a simple 10X oscilloscope probe circuit with an input impedance of $1\,\mathrm {M\Omega }$ and an input capacitance of $1\,\mathrm {pF}$ using $R_{1}=900\,\mathrm {k\Omega }$, $R_{2}=100\,\mathrm {k\Omega }$, $C_{1}=1.11\,\mathrm {pF}$, and $C_{2}=10\,\mathrm {pF}$. Since the pole and zero cancel each other out, the bandwidth of the probe circuit is not limited by its RC values.

Let's look at the frequency response and transient response of this circuit using ngspice.

Simulating the RC Voltage Divider

Let us use the SPICE netlist below:

 1 * Wideband Voltage Divider Circuit
 2 * LPA 05 Aug 2020
 3 
 4 .options savecurrents
 5 
 6 R1		in out		900k
 7 R2		out 0		100k
 8 
 9 C1		in out	 	1.1111p
10 C2		out 0		10p
11 
12 * increase C1 and see what happens
13 R1a		in outa		900k
14 R2a		outa 0		100k
15 
16 C1a		in outa	 	1.6p
17 C2a		outa 0		10p
18 
19 * decrease C1 and see what happens
20 R1b		in outb		900k
21 R2b		outb 0		100k
22 
23 C1b		in outb	 	0.7p
24 C2b		outb 0		10p
25 
26 * input square wave
27 V1		in 0		dc 1 ac 1 pulse(-1 1 0 0.1u 0.1u 5u 0.01m)
28 
29 .control
30 
31 ac dec 10 1 1G
32 plot vdb(out) vdb(outa) vdb(outb) 
33 wrdata testac.dat v(out) v(outa) v(outb)
34 
35 tran 0.01u 0.03m
36 plot v(out) v(outa) v(outb)
37 wrdata testtran.dat v(out) v(outa) v(outb)
38 
39 .endc
40 
41 .end