Difference between revisions of "Passive CMOS Devices"

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{{NumBlk|::|<math>R = \frac{\rho \cdot \ell}{A} = \frac{\rho}{t}\frac{\ell}{w}= R_\mathrm{sh} \frac{\ell}{w}</math>|{{EquationRef|1}}}}
 
{{NumBlk|::|<math>R = \frac{\rho \cdot \ell}{A} = \frac{\rho}{t}\frac{\ell}{w}= R_\mathrm{sh} \frac{\ell}{w}</math>|{{EquationRef|1}}}}
  
Where <math>R_\mathrm{sh}</math> is the ''sheet resistance'' of the layer, <math>\rho</math> is the resistivity of the material, <math>\ell</math> is the length along the direction of the current, and <math>A = w\cdot t</math>, is the cross sectional area normal to the current flow, which is equal to the product of the layer thickness, <math>t</math> and <math>w</math> is the width of the layer perpendicular to the current flow, as shown in Fig. 1.  
+
Where <math>R_\mathrm{sh}=\tfrac{\rho}{t}</math> is the ''sheet resistance'' of the layer, <math>\rho</math> is the resistivity of the material, <math>\ell</math> is the length along the direction of the current, and <math>A = w\cdot t</math>, is the cross sectional area normal to the current flow, which is equal to the product of the layer thickness, <math>t</math> and <math>w</math> is the width of the layer perpendicular to the current flow, as shown in Fig. 1. Note that the resistivity, <math>\rho</math>, and layer thickness, <math>t</math> are technology specific parameters, and are determined by the fabrication process. The designer can specify resistance values by controlling the width, <math>w</math>, and the length, <math>\ell</math>.
  
 
Note that the units of sheet resistance is <math>\mathrm{\Omega/\square}</math> since <math>R_\mathrm{sh}</math> is the resistance of a square, i.e. when <math>\ell = w</math>. Table 1 shows indicative sheet resistance values of the common conductive layers in a CMOS process.
 
Note that the units of sheet resistance is <math>\mathrm{\Omega/\square}</math> since <math>R_\mathrm{sh}</math> is the resistance of a square, i.e. when <math>\ell = w</math>. Table 1 shows indicative sheet resistance values of the common conductive layers in a CMOS process.

Revision as of 23:23, 20 September 2020

Passive devices such as resistors, capacitors, and inductors, are commonly used in biasing circuits, feedback networks, and signal or energy storage blocks. However, these passive devices, when built on fabrication processes that are optimized for transistors, may have characteristics different from their ideal or discrete counterparts. In this module, we examine the behavior of passive devices built alongside CMOS transistors.

Resistors

In standard digital CMOS processes, there is usually no provision for high resistance layers, since resistances are typically deemed bad for digital circuits. But in analog design, we often need well-controlled resistors, with relatively large resistance values.

Sheet Resistance

Figure 1: Layer resistance parameters.

In order to evaluate if a particular layer could be used as to build a resistor, we look to their sheet resistance. Recall that for a resistor:

 

 

 

 

(1)

Where is the sheet resistance of the layer, is the resistivity of the material, is the length along the direction of the current, and , is the cross sectional area normal to the current flow, which is equal to the product of the layer thickness, and is the width of the layer perpendicular to the current flow, as shown in Fig. 1. Note that the resistivity, , and layer thickness, are technology specific parameters, and are determined by the fabrication process. The designer can specify resistance values by controlling the width, , and the length, .

Note that the units of sheet resistance is since is the resistance of a square, i.e. when . Table 1 shows indicative sheet resistance values of the common conductive layers in a CMOS process.

Table 1: Sheet Resistances
Layer Sheet Resistance
Metal
Polysilicon
or Diffusion
-well

An illustrative cross-section of resistors using these layers are shown in Figs. 2 and 3.

Figure 2: Resistors built using semiconductor layers[1].
Figure 3: Resistors built using metal layers[1].
Figure 4: Silicide layers on diffusion and polysilicon layers to reduce the effective sheet resistance[2].

In a CMOS process optimized for digital circuits, the low sheet resistances of the semiconductor layers are due to a low-resistance silicide layer deposited on top of the semiconductor layer, as shown in Fig. 4. In analog CMOS processes, we are usually given the option to place a silicide block, i.e. to prevent the silicide layer from being deposited on specific locations on the die. Table 2 contains illustrative values of the sheet resistance of the semiconductor layers with the silicide block option.

Table 2: Non-Silicided Layer Properties
Layer @
-polysilicon 100 -800 50 50
-polysilicon 180 200 50 50
-diffusion 50 1500 500 -500
-diffusion 100 1600 -500 500
-well 1000 -1500 20,000 30,000

Temperature and Voltage Coefficients

In general, semiconductor resistor values change with temperature and applied voltage, and to describe these changes, we use temperature and voltage coefficients:

 

 

 

 

(2)

Where is the nominal resistance value at some reference temperature , is the temperature coefficient, is the voltage coefficient, is the body voltage coefficient, and are the terminal voltages, and is the bulk or body or substrate voltage.

In semiconductors, we know that the resistivity is a strong function of temperature, roughly due to two mechanisms: (1) increasing the temperature increases the number of free carriers, thus lowering the resistance, resulting in negative temperature coefficients, and (2) this increase in free carriers increases the probability of scattering events or collisions, increasing the effective resistance, resulting in positive temperature coefficients. Thus, depending on which mechanism is dominant, we get positive or negative temperature coefficients.

The voltage coefficient models the changes in resistance values due to the varying depletion region widths caused by the terminal voltages. On the other hand, for the body voltage coefficient, we use the average voltage across the resistor relative to the substrate voltage.

Resistor Matching

Capacitors

Inductors

References

  1. 1.0 1.1 Phillip Allen's slides on Deep Submicron CMOS Technologies
  2. Krishna Saraswat's slides on Polycides, Salicides and Metals Gates.