SFG Butterworth Low-Pass Filter Example

A 5th-order passive low-pass Butterworth filter is shown in Fig. 1. For $f_{-3{\text{dB}}}=10\,\mathrm {MHz}$ and $R_{S}=R_{L}=1\,\mathrm {\Omega }$, we get $C_{1}=C_{5}=9.836\,\mathrm {nF}$, $C_{3}=31.83\,\mathrm {nF}$, and $L_{2}=L_{4}=25.75\,\mathrm {nH}$. To convert this passive RLC filter into its active equivalent, we need to first label all the voltages and currents.

Figure 1: A 5th-order low-pass Butterworth filter.

We can then express the capacitor voltages in terms of its currents to get the integrator form $v_{C,k}={\tfrac {1}{sC_{k}}}\cdot i_{C,k}$ for $k=1,3,5$. Similarly for the inductor currents, we get $i_{L,m}={\tfrac {1}{sL_{m}}}\cdot v_{L,m}$ for $m=2,4$. With the remaining KCL and KVL equations, we can construct the signal flow graph in Fig. 2.

Figure 2: The signal flow graph with integrator forms.

Using a normalizing resistor, $R^{*}$, we can normalize the signal flow graph in Fig. 2 to convert the current nodes into voltage nodes.

Figure 3: The normalized signal flow graph with normalizing resistor $R^{*}$.

After normalization, we can then convert the signal flow graph directly to its equivalent integrator-based circuit, shown in Fig. 4.

Figure 4: The integrator-based active filter implementation.

Each integrator can then be implemented using op-amps, as shown in Fig. 5.

Figure 5: An op-amp-based integrator.

Note that:

$\tau _{k}=R^{*}C_{k}$

(1)

For $k=1,3,5$, and

$\tau _{m}={\frac {L_{m}}{R^{*}}}=R^{*}C_{m}$

(2)

For $m=2,4$. If we choose $R=R^{*}=1\,\mathrm {\Omega }$, we then get the capacitor values for the integrator in Fig. 5 as $C_{1}=C_{5}=9.836\,\mathrm {nF}$, $C_{3}=31.83\,\mathrm {nF}$, and $C_{2}=C_{4}=25.75\,\mathrm {nF}$. However, notice that the integrators require a subtraction at its inputs. We can add amplifiers with a gain of $-1$, but this may not be the best solution.

We can solve this problem by using fully differential amplifiers and integrators.

Differential Integrators

One way to address the need for addition and subtraction is to use fully differential amplifiers, where both inverting and non-inverting paths are already generated, and multiplying a signal by $-1$ can be done by simply re-labeling the outputs, i.e. swapping the label for $v^{+}$ and $v^{-}$. We can then convert the two-input single-ended integration in Fig. 6, with output voltage:

$v_{o}=-{\frac {1}{s\cdot R_{1}C}}\cdot v_{1}-{\frac {1}{s\cdot R_{2}C}}\cdot v_{2}$

(3)

Into its fully-differential equivalent, as shown in Fig. 7 with an output voltage equal to:

$v_{od}=v_{o}^{+}-v_{o}^{-}=-{\frac {1}{s\cdot R_{1}C}}\cdot \left(v_{1}^{+}-v_{1}^{-}\right)-{\frac {1}{s\cdot R_{2}C}}\cdot \left(v_{2}^{+}-v_{2}^{-}\right)$

(4)

Figure 6: A two-input op-amp integrator.

Figure 7: A two-input fully differential op-amp integrator.

Note that swapping $v_{o}^{+}$ and $v_{o}^{-}$ is equivalent to multiplying the output by $-1$, allowing us to perform both addition and subtraction. Additionally, using fully differential circuits reduces power supply noise and increases common-mode rejection.

Using fully differential integrators, we can now construct the active filter, and using this SPICE file, we get the magnitude response in Fig. 8. Note that the first integrator, with time constant $\tau _{1}$, needs three inputs to accommodate $v_{i}$, $v_{2}$, and $v_{3}^{\prime }$. All the other integrators have two-inputs. As expected, the integrator-based active filter matches the response of the passive RLC circuit perfectly.

Figure 8: SPICE simulation of the magnitude response of the active integrator-based filter.

Maximizing Dynamic Range

We can plot the intermediate internal nodes of the active filter, i.e. the outputs of the integrators, as shown in Fig. 9. Notice that the required maximum voltage swings of these nodes differ by quite a bit. Amplifiers with lower maximum output swings will have lower signal-to-noise ratios (SNR), and if the output swings are different, we will need to design and optimize the integrators individually.

Figure 9: SPICE simulation of the magnitude response of the active filter intermediate nodes.

Since we are using amplifiers, we can control the gain of the integrators, and scale the output voltage of the individual amplifiers such that: (1) we maximize the output swing of each amplifier/integrator, and hence the dynamic range/SNR, and (2) make the output swings of all the integrators equal to each other, so we can just use one specification in designing all the integrators, reducing the design effort. Scaling the output node by a factor of $k$ gives us:

${\begin{aligned}k\cdot v_{o}&=k\cdot \left(-{\frac {1}{R_{1}C}}\int v_{1}\cdot dt-{\frac {1}{R_{2}C}}\int v_{2}\cdot dt\right)\\&=-k\cdot {\frac {1}{R_{1}C}}\int v_{1}\cdot dt-k\cdot {\frac {1}{R_{2}C}}\int v_{2}\cdot dt\\&=-{\frac {1}{\left({\frac {R_{1}}{k}}\right)C}}\int v_{1}\cdot dt-{\frac {1}{\left({\frac {R_{2}}{k}}\right)C}}\int v_{2}\cdot dt\end{aligned}}$

(4)

Note that we also have to scale the resistances of the load integrators by $k$ to maintain the same currents $i_{x}$ and $i_{y}$ so that the output swings of these downstream integrators are maintained, as shown in Fig. 10. Thus, Similar to scaling the nodes in a SFG, to scale the integrator output by a factor of $k$, we need to scale the integrator resistances by ${\tfrac {1}{k}}$, and scale the resistance of the load integrators by a factor of $k$.

Figure 10: Scaling the integrator output by a factor of $k$.

Fig. 11 shows the magnitude response of the intermediate nodes after scaling using this SPICE file. Again, because of the presence of active elements, i.e. amplifiers, we can scale the output node as well, as shown in Fig. 12, and generated using this SPICE file.

Figure 11: SPICE simulation after scaling the intermediate nodes.

Figure 12: SPICE simulation after scaling the intermediate nodes and output node.

In this example, we scaled all the integrator outputs to have a maximum swing of 1 (0 dB) relative to the input, but in general we can scale it to have even more gain depending on the application and implementation constraints.

Noise Analysis

Recall from our review of integrators that if we assume the noise of the resistors dominate, the total output integrated noise of the three-input integrator is equal to:

${\overline {v_{o,{\text{T}}}^{2}}}={\frac {3kT}{C}}$

(5)

In our example, the total RMS noise voltage is simulated to be ${\sqrt {\overline {v_{o,{\text{T}}}^{2}}}}=2\,\mathrm {\mu V}$. Depending on the application, this could sufficient, too small, or too large. Consider the case when this noise is too small for our purposes. We can scale the noise up by reducing the capacitance value. To maintain the same integrator time constant, we need to scale the resistors up by the same factor, as seen in Fig. 13.

Figure 13: Scaling the integrator output noise by a factor of $k$.

So if we want to scale up the noise to ${\sqrt {\overline {v_{o,{\text{T}}}^{2}}}}=150\,\mathrm {\mu V}$, we need to scale the capacitors by:

$k=\left({\frac {\sqrt {\overline {v_{o,{\text{T,new}}}^{2}}}}{\sqrt {\overline {v_{o,{\text{T,old}}}^{2}}}}}\right)^{2}=\left({\frac {150\,\mathrm {\mu V} }{2\,\mathrm {\mu V} }}\right)^{2}=5625$

(6)

Note that scaling the noise to the appropriate level can significantly lower the capacitor values and increase the resistance values, saving significant chip area and power, as well as reducing the effect of parasitic elements.