Difference between revisions of "229-A1.1"
Jump to navigation
Jump to search
| (2 intermediate revisions by the same user not shown) | |||
| Line 14: | Line 14: | ||
== Paper Reading == | == Paper Reading == | ||
| − | * T. Skotnicki, J. A. Hutchby, Tsu-Jae King, H. -. P. Wong and F. Boeuf, '''The end of CMOS scaling: toward the introduction of new materials and structural changes to improve MOSFET performance,''' in IEEE Circuits and Devices Magazine, vol. 21, no. 1, pp. 16-26, Jan.-Feb. 2005, doi: 10.1109/MCD.2005.1388765. | + | * T. Skotnicki, J. A. Hutchby, Tsu-Jae King, H. -. P. Wong and F. Boeuf, '''The end of CMOS scaling: toward the introduction of new materials and structural changes to improve MOSFET performance,''' in ''IEEE Circuits and Devices Magazine'', vol. 21, no. 1, pp. 16-26, Jan.-Feb. 2005, doi: 10.1109/MCD.2005.1388765. |
** You can access this paper for free via the UPEEEI VPN service. If you cannot access the IEEE link via the UPEEEI VPN, you can also access this via this [https://inst.cs.berkeley.edu/~n241/sp07/index_files/The%20end%20of%20CMOS%20scaling.pdf link]. | ** You can access this paper for free via the UPEEEI VPN service. If you cannot access the IEEE link via the UPEEEI VPN, you can also access this via this [https://inst.cs.berkeley.edu/~n241/sp07/index_files/The%20end%20of%20CMOS%20scaling.pdf link]. | ||
| − | * C.-H. Jan et al., '''RF CMOS technology scaling in High-k/metal gate era for RF SoC (system-on-chip) applications,''' 2010 International Electron Devices Meeting, San Francisco, CA, 2010, pp. 27.2.1-27.2.4, doi: 10.1109/IEDM.2010.5703431. | + | * C.-H. Jan et al., '''RF CMOS technology scaling in High-k/metal gate era for RF SoC (system-on-chip) applications,''' ''2010 International Electron Devices Meeting'', San Francisco, CA, 2010, pp. 27.2.1-27.2.4, doi: 10.1109/IEDM.2010.5703431. |
** You can access this paper for free via the UPEEEI VPN service. If you cannot access the IEEE link via the UPEEEI VPN, you can also access this via this [https://ece.iisc.ac.in/~banerjee/course_E3237/Upload_files/Intel_32nmRFCMOS.pdf link]. | ** You can access this paper for free via the UPEEEI VPN service. If you cannot access the IEEE link via the UPEEEI VPN, you can also access this via this [https://ece.iisc.ac.in/~banerjee/course_E3237/Upload_files/Intel_32nmRFCMOS.pdf link]. | ||
| Line 23: | Line 23: | ||
== Report Guide == | == Report Guide == | ||
| − | Based on the video you watched, the papers (not limited to the two papers above) you have read, and any other resource that is available to you, write a short (1-2 page) report on what you think would be the key challenges | + | Based on the video you watched, the papers (not limited to the two papers above) you have read, and any other resource that is available to you, write a short (1-2 page) report on what you think would be the key challenges IC designers in general, and RFIC designers in particular, would face in the near future, and why. |
| − | == Submission == | + | === Submission === |
| − | Submit your | + | Submit your report via email before starting Module 2. |
Latest revision as of 00:59, 14 September 2020
- Activity: IC Fabrication
- Instructions: In this activity, you are tasked to
- Watch a short video about integrated circuit (IC) fabrication.
- Read two papers on CMOS scaling.
- Write a short (1-page) report.
- Should you have any questions, clarifications, or issues, please contact your instructor as soon as possible.
- At the end of this activity, the student should be able to:
- Enumerate and explain the key steps and technologies involved in fabricating integrated circuits.
- Explain why there is a concern about the future of CMOS technology.
Video
- Video: Silicon Run I (1996) Youtube link
Paper Reading
- T. Skotnicki, J. A. Hutchby, Tsu-Jae King, H. -. P. Wong and F. Boeuf, The end of CMOS scaling: toward the introduction of new materials and structural changes to improve MOSFET performance, in IEEE Circuits and Devices Magazine, vol. 21, no. 1, pp. 16-26, Jan.-Feb. 2005, doi: 10.1109/MCD.2005.1388765.
- You can access this paper for free via the UPEEEI VPN service. If you cannot access the IEEE link via the UPEEEI VPN, you can also access this via this link.
- C.-H. Jan et al., RF CMOS technology scaling in High-k/metal gate era for RF SoC (system-on-chip) applications, 2010 International Electron Devices Meeting, San Francisco, CA, 2010, pp. 27.2.1-27.2.4, doi: 10.1109/IEDM.2010.5703431.
- You can access this paper for free via the UPEEEI VPN service. If you cannot access the IEEE link via the UPEEEI VPN, you can also access this via this link.
VPN Access
For questions on UPEEEI VPN access, please send an email to EEEI Support: @
Report Guide
Based on the video you watched, the papers (not limited to the two papers above) you have read, and any other resource that is available to you, write a short (1-2 page) report on what you think would be the key challenges IC designers in general, and RFIC designers in particular, would face in the near future, and why.
Submission
Submit your report via email before starting Module 2.
