View source for CoE 197U S2 AY 2022-2023

* '''Introduction to Analog and Digital Integrated Circuit Design'''
* Semester Offered: 2nd semester
* Course Credit: Lecture: 3 units (2 units lecture, 1 unit lab)

== Catalog Description ==
IC Fabrication. CMOS gates. Logical Effort. Interconnect. Memory Elements. MOS Amplifiers. Current Sources. Differential Amplifiers. Operational Transconductance Amplifiers. 

Pre-req: EEE 41 or EEE 131. 5h (2 lec, 3 lab) 3 u.

== Syllabus ==

{| class="wikitable"
|-
! scope="col"| Module
! scope="col"| Topics
! scope="col"| Outcomes
! scope="col"| Resources
! scope="col"| Activities
|-
| style="text-align:center;" colspan="5" | ''Part I: Digital Integrated Circuits''
|-
| style="text-align:center;" | 0
| 
''Feb 13-18''
* CoE 197U Orientation
| 
* Set class expectations, discuss grading system
* Introduction to CoE 197U
| 
* Syllabus [PDF]
|
* Lab orientation
|-
| style="text-align:center;" | 1
| 
''Feb 20-25''
* [[CoE 197U Introduction | Introduction]]
* [[CoE 197U IC Fabrication | IC Fabrication]]
* [[CoE 197U Scaling | Scaling]]
| 
* Identify the key characteristics and non-idealities of a CMOS fabrication process.
* Analyze how these key characteristics and non-idealities change the characteristics of the devices that will be built on it.
| 
* Video: Silicon Run I (1996) [https://www.youtube.com/watch?v=3XTWXRj24GM Youtube link]
* Paolo Gargini's [https://www.dropbox.com/s/6eskh6bwdcuzpsa/1507_11_Paolo%20Overview_Out.pdf presentation] from the 2015 [http://www.itrs2.net/ International Technology Roadmap for Semiconductors] (ITRS) Summer Meeting.
|
* [[CoE197U-A1.1]]: IC Fabrication and Scaling
* [https://drive.google.com/file/d/1GzSEjBMqHtM1USbNVVZdOOy8eDpJhXJ6/view?usp=sharing Lab 01]: Introduction to Digital IC Design (MOS Characterization)
|-
| style="text-align:center;" | 2
| 
''Mar 6-11''
* [[CoE 197U The MOS Transistor | The MOS Transistor]]
* [[CoE 197U The MOS Switch | The MOS Switch]]
* [[CoE 197U CMOS Inverter | The CMOS Inverter]]
| 
* Simplify the analysis of a CMOS inverter using switch-level transistor models.
* Determine key CMOS inverter metrics and understand their significance in the analysis and design process.
| 
* Slides: MOS [[https://drive.google.com/file/d/1H-aBeApfPlgFNqAMoMqIDZSbyDmwHFPf/view?usp=sharing PDF]]
* Slides: CMOS Inverter [[https://drive.google.com/file/d/1H4Dt_YkLFLWvAVurp7ZxcXbJAPw6frR5/view?usp=sharing PDF]]
* Recording: Module Discussion [[https://drive.google.com/file/d/1H5yoNWBSQfp_TSfS6voFygigZTX6G97F/view?usp=sharing Video]]
|
* [https://drive.google.com/file/d/1gVGg0lAjCFwDzgUzz4TIbXgXCw64yl6o/view?usp=sharing Lab 02]: CMOS Inverter
|-
| style="text-align:center;" | 3
| 
''Mar 13-18''
* [[ CoE 197U CMOS Gates | Static CMOS Gates ]]
* [[ CoE 197U Logical Effort | Logical Effort and Delay ]]
| 
* Design CMOS static gates
* Estimate delays of cascaded logic gates
* Design multistage networks for optimal speed
| 
* Slides: CMOS Gates [[https://drive.google.com/file/d/10McCC1megDnllbIMj7rdtBlyZB84QVBh/view?usp=sharing PDF]]
* Slides: Logical Effort [[https://drive.google.com/file/d/10dGqE_NolixkYaL7aUWMlwPaIILprEFg/view?usp=sharing PDF]]
* Additional Slides: LE Example [[https://drive.google.com/file/d/1IvgU-3yIFlPBbj0PAdfdnyrPYkas3qnf/view?usp=sharing PDF]]
|
<!-- * [[CoE197U-A3.1]]: Logical Effort -->
* [https://drive.google.com/file/d/1IgdNWWsXWqQegJP914KjZ7m4zVZ5LEQo/view?usp=sharing HW] Module 3 HW (final extension May 5)
* [https://drive.google.com/file/d/1bHTAunfnUid3HUrl9oINJhUVqcxf2HUo/view?usp=sharing Lab 03]: Static CMOS Gates
|-
| style="text-align:center;" | 4
| 
''Mar 20-25''
* [[ CoE 197U Power and Energy | Power and Energy ]]
* Optional: [[ CoE 197U Interconnects | Interconnects ]]
| 
* Identify sources of power and energy consumption in digital circuits
* Evaluate energy efficient techniques for digital logic using defined metrics
* Model interconnects as parasitic resistances and capacitances and estimate corresponding delay
| 
* Slides: Power and Energy [[https://drive.google.com/file/d/1IiXkv95fMswIMGUNvRdeh4gd0mv32zyT/view?usp=sharing PDF]]
* Slides: Interconnects [PDF]
|
* [https://drive.google.com/file/d/1d32Az_8MDIgj5OxfrF2ouxEzzyTpOGb3/view?usp=sharing Lab 04]: Delay Optimization and Considerations in Digital Design
|-
| style="text-align:center;" | 5
|
''Mar 20-25''
* [[ CoE 197U Memory | Memory Elements ]]
* [[ CoE 197U Timing | Timing ]]
| 
* Enumerate and distinguish different memory element classifications
* Identify timing parameters relevant to memory elements and their effects on sequential circuit timing
* Design and characterize basic memory elements
| 
* Slides: Memory [[https://drive.google.com/file/d/1Im5QU8FoXTTAIr7ah499VN_LVsfKY0uq/view?usp=sharing PDF]]
* Slides: Timing [[https://drive.google.com/file/d/1IlpWLKPaWKP5bqpQP_tKlZuypvrjcdcI/view?usp=sharing PDF]]
* Slides: Optional materials [[https://drive.google.com/file/d/1IkQsL_U9BSwbP1cwL5ntbUB3Tawk_qYM/view?usp=sharing PDF]]
* Video: Module discussion [[https://drive.google.com/file/d/1IwDyzqReLLr5BP8YmKWSXs1daNkBoUMw/view?usp=sharing Link]]
* 2019 Exam: [[https://drive.google.com/file/d/11nFrLUBhYL-glsAPQCNCBJ1gmKH9Nne6/view?usp=sharing PDF]]
|
<!-- * [[CoE197U-A5.1]]: Timing -->
* [https://drive.google.com/file/d/1o2jk_-bh_OMQUXVtHpMyHa2e127UavZz/view?usp=sharing Lab (Optional)]: SRAM
|-
| style="text-align:center;" colspan="5" | ''Part II: Analog Integrated Circuits''
|-
| style="text-align:center;" | 6
|
''Apr 17-22''
* MOS Amplifiers: DC and AC Analysis
|
* Determine the DC operating point of MOS amplifiers.
* Extract the MOS small-signal parameters depending on the DC operating point.
* Analyze MOS amplifiers in the AC and DC domain.
* Derive the two-port network representation of MOS amplifiers.
* Identify the appropriate application of a MOS amplifier topology based on its two-port parameters.
|
* Slides: DC and AC Analysis [https://drive.google.com/file/d/1J5bNkvjyJ5dF0HWpcLABiQq9WOlnyqje/view?usp=sharing PDF] 
* Videos: [https://www.youtube.com/watch?v=4tEYeFiYwWI&list=PL4if6jkKNTz9RgsB4Gq_g374b4oLYOAeH&index=1 Part 1] [https://www.youtube.com/watch?v=lD7ejAl4Ue4&list=PL4if6jkKNTz9RgsB4Gq_g374b4oLYOAeH&index=2 Part 2]
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* [https://drive.google.com/file/d/1qJUb3iom66Uo02n5bMg2TonGcRE-OKIU/view?usp=sharing Lab 05]: Introduction to Analog IC Design (MOS Characterization)
|-
| style="text-align:center;" | 7
|
''Apr 24-29''
* MOS Amplifiers: Frequency Response
|
* Analyze MOS amplifiers in the frequency domain.
* Sketch the Bode plots of the transfer function.
* Estimate the dominant pole using ZVTCA.
|
* Slides: Frequency Response [https://drive.google.com/file/d/1IA9OF95XS4FV852IuIpbY5iy1KquA4VI/view?usp=sharing PDF] 
* Videos: [https://www.youtube.com/watch?v=1AzlCV_AXgg&list=PL4if6jkKNTz9RgsB4Gq_g374b4oLYOAeH&index=3 Part 1] [https://www.youtube.com/watch?v=I3I6CBye0rU&list=PL4if6jkKNTz9RgsB4Gq_g374b4oLYOAeH&index=4 Part 2] [https://www.youtube.com/watch?v=55w6EXRSR1M&list=PL4if6jkKNTz9RgsB4Gq_g374b4oLYOAeH&index=5 Part 3]
|
* [https://drive.google.com/file/d/1qxZYVYwmhjmUJH1Y5JeKc9VQTlU6Y3Oh/view?usp=sharing Lab 06]: Common-Source Amplifier with Resistive Load
|-
| style="text-align:center;" | 8
|
''May 8-13''
* Current Sources
* High-Swing Current Sources
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* Understand ideal and real sources
* Analyze MOS simple current mirror
* Analyze High-swing current sources
| 
* Slides: Current Sources [https://drive.google.com/file/d/19jU1NupCk66ta6Q3tJyWFYDUagqaZCQs/view?usp=sharing PDF]
* Slides: High-Swing Current Sources [https://drive.google.com/file/d/15dsEE2jcVoUNasZmvCOlewN77UxfOieB/view?usp=sharing PDF]
|
* Lab 07: Current Sources
|-
| style="text-align:center;" | 9
| 
''May 15-20''
* [[ CoE 197U MOS Differential Pairs | MOS Differential Pairs ]]
* [[ CoE 197U Two-Stage MOS Operational Transconductance Amplifiers | Two-Stage MOS OTA ]]
| 
* Understand differential circuits
* Analyze MOS differential pairs
* Understand operational amplifier operation
* Analyze Miller Operational Amplifiers
| 
* Slides: MOS Differential Pairs [https://drive.google.com/file/d/10p4T9_5qMXiXPeVU0B0yHmzmtTabiQ43/view?usp=sharing PDF]
* Slides: Miller Op-Amp [https://drive.google.com/file/d/1ARDhJZ5SXZ9aMOgDCBVHqwkQAiG0FLsn/view?usp=sharing PDF]
|
* Lab 08: Differential Amplifier
|-
| style="text-align:center;" | 10
|
''May 22-27''
* Folded Cascode Operational Transconductance Amplifiers
| 
* Identify the different stages in a folded cascode OTA.
* Determine the components and/or parameters that affect the DC operating point of a folded cascode OTA.
* Explain how to design a folded cascode OTA.
| 
* Slides: Folded Cascode [https://drive.google.com/file/d/1Tg0ZyYzh-rQPGdOqmonEXNXNYPkhJ-aW/view?usp=sharing PDF]
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* Lab 09: Design Problem
|-
|}

== References ==
* Rabaey, Chandrakasan, Nikolic, Digital Integrated Circuits, 2ed., Pearson 2002.
* Gray, Hurst, Lewis, Meyer, Analysis & Design of Analog Integrated Circuits, Wiley 2001.
* Johns, Martin, Analog Integrated Circuit Design, Wiley 1997.
* Design of Analog CMOS Integrated Circuits, Behzad Razavi, McGraw-Hill, 2000.
* R. Jacob Baker, Circuit Design, Layout,and Simulation, 4ed., IEEE Press 2019.